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<title>u-boot.git/arch, branch v2025.01-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch?h=v2025.01-rc2</id>
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<updated>2024-11-11T13:25:25Z</updated>
<entry>
<title>Merge tag 'u-boot-rockchip-20241111' of https://source.denx.de/u-boot/custodians/u-boot-rockchip</title>
<updated>2024-11-11T13:25:25Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-11-11T13:25:25Z</published>
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<id>urn:sha1:fdcf06d58d94c40eb02a9c034af613cee08eb3f2</id>
<content type='text'>
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/23280

- Add board:
        rk3328: FriendlyElec NanoPi R2S Plus
        rk3568: Qnap TS433
        rk3588: Cool Pi CM5 GenBook
- Move rk3399_force_power_on_reset to TPL for puma board;
</content>
</entry>
<entry>
<title>rockchip: rk3399: move sysreset-gpio logic to TPL</title>
<updated>2024-11-11T07:14:15Z</updated>
<author>
<name>Quentin Schulz</name>
<email>quentin.schulz@cherry.de</email>
</author>
<published>2024-11-06T11:29:44Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0a17123dedf827f4ca9b158252279adf03906307'/>
<id>urn:sha1:0a17123dedf827f4ca9b158252279adf03906307</id>
<content type='text'>
If TPL_GPIO and TPL_PINCTRL_ROCKCHIP are enabled and a sysreset-gpio is
provided in the TPL Device Tree, this will trigger a system reset
similar to what's currently been done in SPL whenever the RK3399 "warm"
boots. Because there's currently only one user of sysreset-gpio logic,
and TPL is enabled on that board, so let's migrate the logic and that
board to do it in TPL.

There are three reasons for moving this earlier:
- faster boot time as we don't need to reach SPL to be able to reset the
  system on a condition we know is already met in TPL,
- have less code to be impacted by the issue this system reset works
  around (that is, "unclean" SoC registers after a reboot),
- less confusion around the reason for restarting. Indeed when done from
  SPL, the following log can be observed:

"""
U-Boot TPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45)
Channel 0: DDR3, 666MHz
BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
Channel 1: DDR3, 666MHz
BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
256B stride
Trying to boot from BOOTROM
Returning to boot ROM...

U-Boot SPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45 +0100)
Trying to boot from MMC2

U-Boot TPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45)
"""

possibly hinting at an issue within the SPL when loading the fitImage
from MMC2 instead of the normal course of events (a system reset).

Signed-off-by: Quentin Schulz &lt;quentin.schulz@cherry.de&gt;
Reviewed-by: Paul Kocialkowski &lt;paulk@sys-base.io&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>rockchip: tpl: allow to call board/SoC-specific code before DRAM init</title>
<updated>2024-11-11T07:14:15Z</updated>
<author>
<name>Quentin Schulz</name>
<email>quentin.schulz@cherry.de</email>
</author>
<published>2024-11-06T11:29:43Z</published>
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<id>urn:sha1:7461d55ca7d1a55d5f90c5d33501a369eabd4277</id>
<content type='text'>
This defines a weak tpl_board_init function that can be used for running
board/SoC-specific code before the DRAM init happens, similarly to
spl_board_init() for SPL.

Reviewed-by: Paul Kocialkowski &lt;paulk@sys-base.io&gt;
Signed-off-by: Quentin Schulz &lt;quentin.schulz@cherry.de&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>rockchip: rk3399: merge CRU check within rk3399_force_power_on_reset</title>
<updated>2024-11-11T07:14:14Z</updated>
<author>
<name>Quentin Schulz</name>
<email>quentin.schulz@cherry.de</email>
</author>
<published>2024-11-06T11:29:42Z</published>
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<id>urn:sha1:b21fd44c84fd5053a350de6138fb832839c04b67</id>
<content type='text'>
To prepare to support forcing power on reset from TPL which would have
the exact same logic, just in an earlier stage, let's merge the CRU
check that triggers the power on reset with the rest of the logic.

Reviewed-by: Paul Kocialkowski &lt;paulk@sys-base.io&gt;
Signed-off-by: Quentin Schulz &lt;quentin.schulz@cherry.de&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>board: rockchip: Add FriendlyElec NanoPi R2S Plus</title>
<updated>2024-11-11T07:14:14Z</updated>
<author>
<name>Jonas Karlman</name>
<email>jonas@kwiboo.se</email>
</author>
<published>2024-11-01T22:21:30Z</published>
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<id>urn:sha1:3133b7c645157846590f6fc16e26f54d70f5e1d6</id>
<content type='text'>
The FriendlyElec NanoPi R2S Plus is a single-board computer based on
Rockchip RK3328 SoC. It features e.g. 1 GB DDR4 RAM, 32 GB eMMC,
SD-card, 2x GbE LAN, optional M.2 SDIO Wi-Fi and 2x USB 2.0 host.

Features tested on a NanoPi R2S Plus 2309:
- SD-card boot
- eMMC boot
- Ethernet
- USB gadget
- USB host

Signed-off-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>board: rockchip: Add support for rk3588 GenBook</title>
<updated>2024-11-11T07:14:14Z</updated>
<author>
<name>Andy Yan</name>
<email>andyshrk@163.com</email>
</author>
<published>2024-11-04T12:23:00Z</published>
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<id>urn:sha1:dfcd4afd4cc0801358f9741d6d6388928a091498</id>
<content type='text'>
Add support for Cool Pi GenBook, it works as a carrier board
connect with CM5 SOM.

Specification:
- Rockchip RK3588
- LPDDR5X 8/32 GB
- eMMC 64 GB
- HDMI Type A out x 1
- USB 3.0 Host x 1
- USB-C 3.0 with DisplayPort AltMode
- PCIE M.2 E Key for RTL8852BE Wireless connection
- PCIE M.2 M Key for NVME connection
- eDP panel with 1920x1080

Tested by Armbian boot on USB disk.

Change-Id: I4d9b8572dc7c400077dde666633f3fea1b47dd03
Signed-off-by: Andy Yan &lt;andyshrk@163.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>board: rockchip: add support for Qnap TS433 devices</title>
<updated>2024-11-11T07:14:14Z</updated>
<author>
<name>Heiko Stuebner</name>
<email>heiko@sntech.de</email>
</author>
<published>2024-10-28T19:00:34Z</published>
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<id>urn:sha1:d3cacb79e7062772e54cb4a2f5a23f873a630b0e</id>
<content type='text'>
The Qnap TS433 is a 4-bay NAS based around the RK3568.

Two SATA bays are connected to the RK3568's own SATA controllers while
the other two are connected to a JMicron SATA controller living on the
PCIe bus.

It provides one 2.5Gb and one 1Gb ethernet port as well as 3 usb ports.

Signed-off-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>board: hoperun: Switch to use complete DTS files from upstream DTS</title>
<updated>2024-11-10T18:38:46Z</updated>
<author>
<name>Lad Prabhakar</name>
<email>prabhakar.mahadev-lad.rj@bp.renesas.com</email>
</author>
<published>2024-11-04T13:50:12Z</published>
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<id>urn:sha1:5fb5ed2f78656f8f562de37037d58c10b4cc456b</id>
<content type='text'>
For upstream Linux kernel we use below DTBs for HiHope boards:
- r8a774a1-hihope-rzg2m-ex.dtb
- r8a774e1-hihope-rzg2h-ex.dtb
- r8a774b1-hihope-rzg2n-ex.dtb

Update the CONFIG_OF_LIST to match the above. Now that we have switched
upstream DTS, drop deleting the nodes and also rename the
r8a774*-u-boot.dtsi files to r8a774*-ex-u-boot.dtsi to match the OF_LIST
files so that the `bootph-all` property gets applied to required nodes
in upstream DTS.

Signed-off-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Signed-off-by: Chris Paterson &lt;chris.paterson2@renesas.com&gt;
</content>
</entry>
<entry>
<title>arm: renesas: Fix RZ/G2L GICR base address</title>
<updated>2024-11-10T18:36:54Z</updated>
<author>
<name>Paul Barker</name>
<email>paul.barker.ct@bp.renesas.com</email>
</author>
<published>2024-11-01T14:20:16Z</published>
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<id>urn:sha1:9d81a9ff990bae1bcf08ae5b888e0b6e12d1b58b</id>
<content type='text'>
When support for the Renesas RZ/G2L SoC was added, the GICR base address
for CPU1 was accidentally used. We should instead supply the GICR base
address for CPU0 so that interrupts are correctly configured for the
CPU core that U-Boot is actually using.

Fixes: 387d4275ab0e ("arm: rmobile: Add basic RZ/G2L family support")
Signed-off-by: Paul Barker &lt;paul.barker.ct@bp.renesas.com&gt;
</content>
</entry>
<entry>
<title>ARM: dts: Drop unused RZ/G2L devicetrees</title>
<updated>2024-11-10T18:36:38Z</updated>
<author>
<name>Paul Barker</name>
<email>paul.barker.ct@bp.renesas.com</email>
</author>
<published>2024-10-30T14:51:36Z</published>
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<id>urn:sha1:db3b17db5c67936f50a0bb2f6b12870320b870f6</id>
<content type='text'>
We are now using the dts/upstream subtree for the RZ/G2L SoC family so
we can drop unused devicetree files from arch/arm/dts.

Signed-off-by: Paul Barker &lt;paul.barker.ct@bp.renesas.com&gt;
Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
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