Disable incorrectly enabled SCIF1 in Renesas R-Car X5H R8A78000 SoC DT.
The SCIF1 should be enabled on board DT level in case it is needed, but
should be disabled in SoC DT by default. This had no adverse effect on
the currently upstream platforms, because those managed to probe only
the HSCIF0 device and SCIF1 was ignored.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

u-boot-dtb.bin is built by concatenating u-boot-nodtb.bin and u-boot.dtb.
u-boot-nodtb.bin, in turn, is generated by objcopy'ing the contents of
u-boot (U-Boot in ELF format) into a raw file.

In order to find the bundled FDT (u-boot.dtb), the code in lib/fdtdec.c
uses the _end symbol. Platform-specific linker scripts ensure that _end is
8-byte aligned, which is required by libfdt.

For the PowerPC MPC83xx platform, the ALIGN(8) directive was outside a
section, with the unfortunate effect that the potentially generated padding
bytes would not be copied by objcopy. This resulted in a discrepancy
between the _end symbol on the one hand, and the size of u-boot-nodtb.bin
and thus the starting location of the actual FDT on the other side. Under
these conditions, the FDT could not be found and boot would fail early.

This commit fixes it by moving the ALIGN(8) into the __u_boot_list section,
which is non-empty and thus copied into u-boot-nodtb.bin.

Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Reviewed-by: Tom Rini <trini@konsulko.com>

The msg.c file uses EIO macro defined in errno.h , include errno.h
to avoid build failure:

"
arch/arm/mach-bcm283x/msg.c: In function 'bcm2835_power_on_module':
arch/arm/mach-bcm283x/msg.c:73:25: error: 'EIO' undeclared (first use in this function)
   73 |                 return -EIO;
      |                         ^~~
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Commit bb6f3c0f7634 ("armv7: ls102xa: Update SCFG_QSPI_CLKSEL value")
broke the SPI boot on the LS1021ATSN board (ls1021atsn_qspi_defconfig)
at least.

The commit message reads
   Update SCFG_QSPI_CLKSEL value : 0xC -> 0x5
   which means ClusterPLL/16

The original submitted patch had the following description:
   Value 0xC is reserved. Replace it with correct value 0x5 which
   is ClusterPLL/16

Unfortunatly, the little information which was there, was stripped even
further. Why is 0x5 the "correct" value? In fact, it seems that the
upper bit is just ignored and thus the value 0xC translates to 0x4 which
is ClusterPLL/20. This, will result in a SPI clock of 60MHz (if the PLL
is clocked at 1.2GHz). But even that is too much for the (default) 03h
read opcode (max 50MHz). Set the value to ClusterPLL/24 which is 50MHz.

Link: https://lore.kernel.org/r/1568804284-25162-1-git-send-email-kuldeep.singh@nxp.com/
Fixes: bb6f3c0f7634 ("armv7: ls102xa: Update SCFG_QSPI_CLKSEL value")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Since switching to DM_SERIAL 'stdout-path' seems to be necessary.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

The PCIe Controllers in the K3 SoCs have 4 GB Address Windows in the
64-bit address space to map System (CPU) Addresses to PCIe Bus Addresses.
The physical addresses for these Address Windows across PCIe instances
across SoCs is as follows:

+--------+----------------+----------------+----------------+----------------+
| SoC    | PCIe0          | PCIe1          | PCIe2          | PCIe3          |
+--------+----------------+----------------+----------------+----------------+
| AM64   | 0x6_0000_0000  | NA             | NA             | NA             |
| J722S  | 0x6_0000_0000  | NA             | NA             | NA             |
| AM68   | NA             | 0x41_0000_0000 | NA             | NA             |
| J7200  | NA             | 0x41_0000_0000 | NA             | NA             |
| J721S2 | NA             | 0x41_0000_0000 | NA             | NA             |
| J742S2 | 0x40_0000_0000 | 0x41_0000_0000 | NA             | NA             |
| AM69   | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 |
| J721E  | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 |
| J784S4 | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 |
+--------+----------------+----------------+----------------+----------------+

Two regions for a 1:1 mapping from virtual addresses to physical addresses
catering to all of the above will be required, which are:
1. For AM64 and J722S SoCs
=> Start: 0x6_0000_0000 Size: 0x1_0000_0000
2. For AM68, AM69, J7200, J721E, J721S2, J742S2 and J784S4 SoCs
=> Start: 0x40_0000_0000 Size: 0x4_0000_0000

Since the 'Flash Peripherals' region from 0x5_0000_0000 to 0x8_7FFF_FFFF
includes the mapping for AM64 and J722S SoCs, only the second region
mentioned above needs to be added.

Hence, add the region to support 64-bit address space for PCIe.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Fixes: 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")

After years of developing the ADI ADSP platform, Timesys was purchased
by another company and is no longer contracted to maintain the platform.

Signed-off-by: Philip Molloy <philip.molloy@analog.com>
Reviewed-by: Greg Malysa <malysagreg@gmail.com>

- Assorted platform and video driver updates

STM32 update:
_ Add STM32MP21 support (board, machine, cmd_stm32key, cmd_stboard, rifsc)
_ pinctrl: stm32 : various update
_ stm32prog: clean stm32prog_data struct
_ stm32mp2: Fix array bound check in setup_boot_mode()
_ stm32mp2: Update dynamically DDR size in MMU table
_ rifsc: various fixes

Secure state must be checked before handling semaphores,
otherwise it can cause an IAC.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>