u-boot.git/board/AndesTech, branch master

andes: Unify naming policy for Andes related source

2024-05-14T10:50:47+00:00

Signed-off-by: Leo Yu-Chi Liang

spl: riscv: falcon: move fdt blob to specified address

2024-01-31T08:51:03+00:00

In Falcon Boot mode, the fdt blob should be move to the RAM from
kernel BSS section. To avoid being cleared by BSS initialisation.
SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies.

Signed-off-by: Randolph 
Reviewed-by: Leo Yu-Chi Liang

andes: ae350: Save cpu name to env

2023-12-27T09:29:11+00:00

Detect CPU name through marchid and then save it to env.

Signed-off-by: Leo Yu-Chi Liang 
Reviewed-by: Yu Chien Peter Lin

andes: ae350: Implement cache switch via Kconfig

2023-12-27T09:29:07+00:00

Kconfig provides SYS_[I|D]CACHE_OFF config options to switch off caches.
Provide the corresponding implementation to the options.

Signed-off-by: Leo Yu-Chi Liang 
Reviewed-by: Yu Chien Peter Lin

riscv: Remove common.h usage

2023-10-24T20:34:45+00:00

We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini 
Reviewed-by: Rick Chen

ae350: Update defconfig list

2023-10-23T15:40:44+00:00

Update the list of defconfigs, this was missed with the last pull
request of the u-boot-riscv tree.

Signed-off-by: Tom Rini

riscv: spl: andes: Move the DTB in front of kernel

2023-10-19T09:29:33+00:00

Originally, u-boot SPL will place the DTB directly after the kernel,
but the size of the kernel does not include the BSS section, This
means that u-boot SPL places the DTB in the kernel BSS section causing
the DTB to be cleared by the kernel BSS initialisation.

Moving the DTB in front of the kernel can avoid this error.

Signed-off-by: Randolph 
Reviewed-by: Leo Yu-Chi Liang

configs: andes: add vender prefix for target name

2023-10-04T10:00:51+00:00

Modify "CONFIG_TARGET_AE350" to "CONFIG_TARGET_ANDES_AE350"

Signed-off-by: Randolph 
Reviewed-by: Tom Rini

riscv: Rename Andes cpu and board names

2023-02-17T11:07:48+00:00

The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.

Signed-off-by: Leo Yu-Chi Liang 
Reviewed-by: Yu Chien Peter Lin 
Reviewed-by: Rick Chen

board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init()

2023-02-17T11:07:48+00:00

The L2-cache is not enabled currently, the enbale_caches() will call
the v5l2_enable() callback to enable it in SPL.

Signed-off-by: Yu Chien Peter Lin 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Rick Chen