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<title>u-boot.git/board/AndesTech, branch v2020.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>riscv: ax25-ae350: Use generic memory size setup</title>
<updated>2019-12-10T00:23:10+00:00</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2019-11-14T05:52:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7e24518c904d9cab8185a1248a24e86c4ceb19ae'/>
<id>7e24518c904d9cab8185a1248a24e86c4ceb19ae</id>
<content type='text'>
To get memory size from device tree instead of
get_ram_size(). This can avoid memory access fault
in U-Boot proper after PMP configurations in OpenSBI.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: KC Lin &lt;kclin@andestech.com&gt;
Cc: Alan Kao &lt;alankao@andestech.com&gt;
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<pre>
To get memory size from device tree instead of
get_ram_size(). This can avoid memory access fault
in U-Boot proper after PMP configurations in OpenSBI.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: KC Lin &lt;kclin@andestech.com&gt;
Cc: Alan Kao &lt;alankao@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: ax25-ae350: add SPL configuration</title>
<updated>2019-12-10T00:23:10+00:00</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2019-11-14T05:52:22+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cd61e86e6d2a86b3affd90eeae3f5c97fe990b04'/>
<id>cd61e86e6d2a86b3affd90eeae3f5c97fe990b04</id>
<content type='text'>
This patch provides four configurations which can support U-Boot SPL
to boot from RAM or FLASH and then boot FIT image including OpenSBI
FW_DYNAMIC firmware and U-Boot proper images from RAM or MMC boot devices.

With ae350_rv[32|64]_spl_defconfigs:

U-Boot SPL will be loaded by gdb or FSBL and runs in RAM in machine mode
and then load FIT image from RAM device on AE350.

With ae350_rv[32|64]_spl_xip_defconfigs:

U-Boot SPL can be burned into SPI flash and run in flash in machine mode
and then load FIT image from SPI flash or MMC device on AE350.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: KC Lin &lt;kclin@andestech.com&gt;
Cc: Alan Kao &lt;alankao@andestech.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch provides four configurations which can support U-Boot SPL
to boot from RAM or FLASH and then boot FIT image including OpenSBI
FW_DYNAMIC firmware and U-Boot proper images from RAM or MMC boot devices.

With ae350_rv[32|64]_spl_defconfigs:

U-Boot SPL will be loaded by gdb or FSBL and runs in RAM in machine mode
and then load FIT image from RAM device on AE350.

With ae350_rv[32|64]_spl_xip_defconfigs:

U-Boot SPL can be burned into SPI flash and run in flash in machine mode
and then load FIT image from SPI flash or MMC device on AE350.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: KC Lin &lt;kclin@andestech.com&gt;
Cc: Alan Kao &lt;alankao@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: ae350: use the v5l2 driver to configure the cache</title>
<updated>2019-09-03T01:31:03+00:00</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2019-08-28T10:46:07+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=edf0acb3b462732cc236f2a8d00abb82abebf38d'/>
<id>edf0acb3b462732cc236f2a8d00abb82abebf38d</id>
<content type='text'>
Find the UCLASS_CACHE driver to configure the cache controller's
settings.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: KC Lin &lt;kclin@andestech.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
<content type='xhtml'>
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<pre>
Find the UCLASS_CACHE driver to configure the cache controller's
settings.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: KC Lin &lt;kclin@andestech.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: configs: AE350 will use CONFIG_OF_SEPARATE when boots from flash</title>
<updated>2019-05-09T08:46:46+00:00</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2019-04-30T05:49:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d8fc1ef2f0b4b759181fe5fa3c5c64af538cef85'/>
<id>d8fc1ef2f0b4b759181fe5fa3c5c64af538cef85</id>
<content type='text'>
When AE350 boots from flash, use CONFIG_OF_SEPARATE instead of
CONFIG_OF_BOARD.

Also remove unused code about prior_stage_fdt_address.
And modify CONFIG_SYS_FDT_BASE as flash address.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: Greentime Hu &lt;greentime@andestech.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
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<pre>
When AE350 boots from flash, use CONFIG_OF_SEPARATE instead of
CONFIG_OF_BOARD.

Also remove unused code about prior_stage_fdt_address.
And modify CONFIG_SYS_FDT_BASE as flash address.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: Greentime Hu &lt;greentime@andestech.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: configs: Support AE350 SMP booting from flash flow</title>
<updated>2019-05-09T08:46:46+00:00</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2019-05-09T02:20:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e7e47f6391d13bd7e6d5dd705c548d0260a88c55'/>
<id>e7e47f6391d13bd7e6d5dd705c548d0260a88c55</id>
<content type='text'>
Add two defconfigs to support AE350 SMP booting from flash.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: Greentime Hu &lt;greentime@andestech.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add two defconfigs to support AE350 SMP booting from flash.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: Greentime Hu &lt;greentime@andestech.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: ae350: enable SMP</title>
<updated>2019-04-08T01:45:08+00:00</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2019-04-02T07:56:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=076b845893f3bb59dfad80b012d28191c19e2f7b'/>
<id>076b845893f3bb59dfad80b012d28191c19e2f7b</id>
<content type='text'>
Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: Greentime Hu &lt;greentime@andestech.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
</content>
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<pre>
Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: Greentime Hu &lt;greentime@andestech.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: configs: Rename ax25-ae350 defconfig</title>
<updated>2018-12-18T05:25:55+00:00</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2018-12-18T03:02:27+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ab3f92dee69b863e1fc50756abfb3df6febd37fd'/>
<id>ab3f92dee69b863e1fc50756abfb3df6febd37fd</id>
<content type='text'>
Remove cpu name from the defconfig naming.
Because other cpus maybe run on AE350 platform.
So only use platfrom name in defconfig naming
will be better.

Also sync MAINTAINERS:
Rename
a25-ae350_32_defconfig as ae350_rv32_defconfig
ax25-ae350_64_defconfig as ae350_rv64_defconfig

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: Greentime Hu &lt;greentime@andestech.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
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<pre>
Remove cpu name from the defconfig naming.
Because other cpus maybe run on AE350 platform.
So only use platfrom name in defconfig naming
will be better.

Also sync MAINTAINERS:
Rename
a25-ae350_32_defconfig as ae350_rv32_defconfig
ax25-ae350_64_defconfig as ae350_rv64_defconfig

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: Greentime Hu &lt;greentime@andestech.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: ax25: Hide the ax25-specific Kconfig option</title>
<updated>2018-12-18T01:56:26+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2018-12-12T14:12:28+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=44fe795c149cac67a6dbc12a16f7ec5d813b9523'/>
<id>44fe795c149cac67a6dbc12a16f7ec5d813b9523</id>
<content type='text'>
There is no need to expose RISCV_NDS to the Kconfig menu as it is
an ax25-specific option. Introduce a dedicated Kconfig option for
the cache ops of ax25 platform and use that to guard the cache ops.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
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<pre>
There is no need to expose RISCV_NDS to the Kconfig menu as it is
an ax25-specific option. Introduce a dedicated Kconfig option for
the cache ops of ax25 platform and use that to guard the cache ops.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: ax25-ae350: Pass dtb address to u-boot with a1 register</title>
<updated>2018-12-05T06:14:16+00:00</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2018-12-03T09:48:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=48cbf6246052de10d35b616b5efb2f783904a49d'/>
<id>48cbf6246052de10d35b616b5efb2f783904a49d</id>
<content type='text'>
ax25-ae350 use CONFIG_OF_BOARD via a2 and CONFIG_SYS_SDRAM_BASE
to boot from ram which allow the board to override the fdt
address originally.

But after this patch
riscv: save hart ID and device tree passed by prior boot stage
It provide prior_stage_fdt_address which offer a temporary
memory address to keep the dtb address passing from loader(gdb)
to u-boot with a1.

So passing via a2 and CONFIG_SYS_SDRAM_BASE is redundant and
can be removed. And it also somehow may corrupted BBL if it
was be arranged in CONFIG_SYS_SDRAM_BASE.

In board_fdt_blob_setup()
When boting from ram:
prior_stage_fdt_address will be use to reserved dtb temporarily.

When booting from ROM:
dtb will be pre-burned in CONFIG_SYS_FDT_BASE, if it is flash base.
Or CONFIG_SYS_FDT_BASE maybe a memory map space (NOT RAM or ROM)
which is provided by HW.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: Greentime Hu &lt;greentime@andestech.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
ax25-ae350 use CONFIG_OF_BOARD via a2 and CONFIG_SYS_SDRAM_BASE
to boot from ram which allow the board to override the fdt
address originally.

But after this patch
riscv: save hart ID and device tree passed by prior boot stage
It provide prior_stage_fdt_address which offer a temporary
memory address to keep the dtb address passing from loader(gdb)
to u-boot with a1.

So passing via a2 and CONFIG_SYS_SDRAM_BASE is redundant and
can be removed. And it also somehow may corrupted BBL if it
was be arranged in CONFIG_SYS_SDRAM_BASE.

In board_fdt_blob_setup()
When boting from ram:
prior_stage_fdt_address will be use to reserved dtb temporarily.

When booting from ROM:
dtb will be pre-burned in CONFIG_SYS_FDT_BASE, if it is flash base.
Or CONFIG_SYS_FDT_BASE maybe a memory map space (NOT RAM or ROM)
which is provided by HW.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: Greentime Hu &lt;greentime@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-riscv</title>
<updated>2018-11-26T20:52:39+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-11-26T18:45:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ef0b75d3d8afccebd3b9822de6bcae358d4bc0e3'/>
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<pre>
</pre>
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</entry>
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