u-boot.git/board/AndesTech, branch v2024.01

riscv: Remove common.h usage

2023-10-24T20:34:45Z

We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini Reviewed-by: Rick Chen

ae350: Update defconfig list

2023-10-23T15:40:44Z

Update the list of defconfigs, this was missed with the last pull request of the u-boot-riscv tree. Signed-off-by: Tom Rini

riscv: spl: andes: Move the DTB in front of kernel

2023-10-19T09:29:33Z

Originally, u-boot SPL will place the DTB directly after the kernel, but the size of the kernel does not include the BSS section, This means that u-boot SPL places the DTB in the kernel BSS section causing the DTB to be cleared by the kernel BSS initialisation. Moving the DTB in front of the kernel can avoid this error. Signed-off-by: Randolph Reviewed-by: Leo Yu-Chi Liang

configs: andes: add vender prefix for target name

2023-10-04T10:00:51Z

Modify "CONFIG_TARGET_AE350" to "CONFIG_TARGET_ANDES_AE350" Signed-off-by: Randolph Reviewed-by: Tom Rini

riscv: Rename Andes cpu and board names

2023-02-17T11:07:48Z

The current ae350-related defconfigs could also support newer Andes CPU IP, so modify the names of CPU from ax25 to andesv5, and board name from ax25-ae350 to ae350. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin Reviewed-by: Rick Chen

board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init()

2023-02-17T11:07:48Z

The L2-cache is not enabled currently, the enbale_caches() will call the v5l2_enable() callback to enable it in SPL. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen

riscv: ae350: support OpenSBI 1.0+ which enable FW_PIC

2023-02-01T08:17:53Z

Original OpenSBI (without FW_PIC) will relocate itself from 0x1000000 to 0x0. After OpenSBI added FW_PIC codes, it will not relocate any more and always run at 0x1000000. Hence, it may overlap with Kernel memory region. So it is necessary to change OpenSBI address from 0x1000000 to 0x0. More details can refer to commit cb052d771200 ("riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+") Signed-off-by: Rick Chen Reviewed-by: Samuel Holland Reviewed-by: Bin Meng

riscv: ae350: Check firmware_fdt_addr header

2022-10-20T07:26:31Z

Check firmware_fdt_addr header to see if it is a valid fdt blob. Signed-off-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang

riscv: ae350: Fix XIP config boot failure

2022-08-11T10:46:07Z

The booting flow is SPL -> OpenSBI -> U-Boot. The boot hart may change after OpenSBI and may not always be hart0, so wrap the related branch instruction with M-MODE. Current DTB setup for XIP is not valid. There is no chance for CONFIG_SYS_FDT_BASE, the DTB address used in XIP mode, to be returned. Fix this. Fixes: 2e8d2f88439d ("riscv: Remove OF_PRIOR_STAGE from RISC-V boards") Signed-off-by: Rick Chen Signed-off-by: Leo Yu-Chi Liang

ax25-ae350: Move CONFIG_SYS_FDT_BASE to Kconfig

2022-06-06T16:09:29Z

The address where the device tree will be passed in to U-Boot at is now moved to the Kconfig file. If this is user configurable, it needs to be exposed rather than hidden, and should probably be renamed as well. Reviewed-by: Rick Chen Signed-off-by: Tom Rini