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<title>u-boot.git/board/ads5121, branch v2009.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board/ads5121?h=v2009.01</id>
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<updated>2008-11-18T22:13:16Z</updated>
<entry>
<title>Align end of bss by 4 bytes</title>
<updated>2008-11-18T22:13:16Z</updated>
<author>
<name>Selvamuthukumar</name>
<email>selva.muthukumar@e-coninfotech.com</email>
</author>
<published>2008-10-16T17:24:03Z</published>
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<id>urn:sha1:9b827cf1720acda2473afa516956eab6f7cca9a1</id>
<content type='text'>
Most of the bss initialization loop increments 4 bytes
at a time. And the loop end is checked for an 'equal'
condition. Make the bss end address aligned by 4, so
that the loop will end as expected.

Signed-off-by: Selvamuthukumar &lt;selva.muthukumar@e-coninfotech.com&gt;
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>rename CFG_ macros to CONFIG_SYS</title>
<updated>2008-10-18T19:54:03Z</updated>
<author>
<name>Jean-Christophe PLAGNIOL-VILLARD</name>
<email>plagnioj@jcrosoft.com</email>
</author>
<published>2008-10-16T13:01:15Z</published>
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<id>urn:sha1:6d0f6bcf337c5261c08fabe12982178c2c489d76</id>
<content type='text'>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</content>
</entry>
<entry>
<title>ADS5121: Fix NOR and CPLD ALE timing for rev 2 silicon</title>
<updated>2008-08-28T19:36:43Z</updated>
<author>
<name>John Rigby</name>
<email>jrigby@freescale.com</email>
</author>
<published>2008-08-28T19:17:07Z</published>
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<id>urn:sha1:8a490422bed685c9491274ec997f62061d88620b</id>
<content type='text'>
MPC5121 rev 2 silicon has a new register for controlling how long
CS is asserted after deassertion of ALE in multiplexed mode.

The default is to assert CS together with ALE.  The alternative
is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE.

The default is wrong for the NOR flash and CPLD on the ADS5121.

This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD)
it does so conditionally based on silicon rev 2.0 or greater.

Signed-off-by: Martha J Marx &lt;mmarx@silicontkx.com&gt;
Signed-off-by: John Rigby &lt;jrigby@freescale.com&gt;
</content>
</entry>
<entry>
<title>mpc5121: Move iopin features from board specific to common files.</title>
<updated>2008-08-06T02:45:34Z</updated>
<author>
<name>Kenneth Johansson</name>
<email>kenneth@southpole.se</email>
</author>
<published>2008-07-15T10:13:38Z</published>
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<id>urn:sha1:6689484ccd43189322aaa5a1c6cd02cdd511ad7d</id>
<content type='text'>
And in the process eliminate some duplicate register defines.

Signed-off-by: Kenneth Johansson &lt;kenneth@southpole.se&gt;
</content>
</entry>
<entry>
<title>Prepare v1.3.4-rc1: Code cleanup, update CHANGELOG, sort Makefile</title>
<updated>2008-07-15T20:22:44Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2008-07-15T20:22:44Z</published>
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<id>urn:sha1:699f05125509249072a0b865c8d35520d97cd501</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>ADS5121: Fix (delete) incorrect ads5121_diu_init() prototype</title>
<updated>2008-07-13T17:48:26Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2008-07-13T17:48:26Z</published>
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<id>urn:sha1:0f9d5f6d6e814907794995c6a22af752040c35d9</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>fix DIU for small screens</title>
<updated>2008-07-12T19:34:15Z</updated>
<author>
<name>Kenneth Johansson</name>
<email>kenneth@southpole.se</email>
</author>
<published>2008-07-12T19:18:34Z</published>
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<id>urn:sha1:f889265753ddf4465d9d580827bb9289bfac55d6</id>
<content type='text'>
The DIU_DIV register is 8 bit not 5 bit. This prevented large DIV values
so it was not possible to set a slow pixel clock and thus prevented
display on small screens.

Signed-off-by: Kenneth Johansson &lt;kenneth@southpole.se&gt;
Acked-by: John Rigby &lt;jrigby@freescale.com&gt;
</content>
</entry>
<entry>
<title>ADS5121 cleanup compile warnings</title>
<updated>2008-07-12T19:33:59Z</updated>
<author>
<name>John Rigby</name>
<email>jrigby@freescale.com</email>
</author>
<published>2008-07-11T20:44:09Z</published>
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<id>urn:sha1:b60b8573875e650e4c69be667bfc88d3ed474a7c</id>
<content type='text'>
board/ads5121/iopin.c
    Replace bit fields in struct iopin_t with a single
    field and intialize it via plain old macros.
    This fixes the type pun warnings and makes the code
    more readable.

board/ads5121/ads5121.c
    Add include iopin.h to ads5121.c for the iopin_initialize
    prototype.

    Add an extern void ads5121_diu_init(void)

Signed-off-by: John Rigby &lt;jrigby@freescale.com&gt;
</content>
</entry>
<entry>
<title>Fix some more print() format errors.</title>
<updated>2008-07-10T23:16:00Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2008-07-10T23:16:00Z</published>
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<id>urn:sha1:9b55a2536919f4de1bb1044e6eb8262c2f53bc96</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>Configuration changes for ADS5121 Rev 3</title>
<updated>2008-07-10T17:36:42Z</updated>
<author>
<name>Martha Marx</name>
<email>mmarx@silicontkx.com</email>
</author>
<published>2008-05-29T18:23:25Z</published>
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<id>urn:sha1:f31c49db2a5e076f415c0785eb37f67f2faa5fc8</id>
<content type='text'>
ADS5121 Rev 3 board is now the default config

config targets are now

ads5121_config
    Rev 3 board with
	PCI
	M41T62 on board RTC
	512MB DRAM

ads5121_rev2_config
    Rev 2 board with
	No PCI
	256MB DRAM

Signed-off-by: Martha Marx &lt;mmarx@silicontkx.com&gt;
Acked-by: Grant Likely &lt;grant.likely@secretlab.ca&gt;
Acked-by: John Rigby &lt;jrigby@freescale.com&gt;
</content>
</entry>
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