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<title>u-boot.git/board/advantech, branch v2017.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>board: advantech: dms-ba16: apply the proper register setting to fix the voltage peak issue</title>
<updated>2017-04-12T16:05:01+00:00</updated>
<author>
<name>Yung-Ching LIN</name>
<email>yungching0725@gmail.com</email>
</author>
<published>2017-03-28T17:51:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fab70acf83c36eb06612f9c43083b7c3f13e428b'/>
<id>fab70acf83c36eb06612f9c43083b7c3f13e428b</id>
<content type='text'>
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance test

Signed-off-by: Ken Lin &lt;yungching0725@gmail.com&gt;
Acked-by: Akshay Bhat &lt;akshay.bhat@timesys.com&gt;
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<pre>
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance test

Signed-off-by: Ken Lin &lt;yungching0725@gmail.com&gt;
Acked-by: Akshay Bhat &lt;akshay.bhat@timesys.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>board: advantech: dms-ba16: fix AR8033 reset timing issue</title>
<updated>2017-04-12T16:04:53+00:00</updated>
<author>
<name>Yung-Ching LIN</name>
<email>yungching0725@gmail.com</email>
</author>
<published>2017-03-28T17:51:24+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0254006b29fcb960ef8c3188eab12a39845719f0'/>
<id>0254006b29fcb960ef8c3188eab12a39845719f0</id>
<content type='text'>
Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet

Signed-off-by: Ken Lin &lt;yungching0725@gmail.com&gt;
Acked-by: Akshay Bhat &lt;akshay.bhat@timesys.com&gt;
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<pre>
Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet

Signed-off-by: Ken Lin &lt;yungching0725@gmail.com&gt;
Acked-by: Akshay Bhat &lt;akshay.bhat@timesys.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>board: advantech: dms-ba16: add the PMIC configuration support</title>
<updated>2017-04-12T16:04:44+00:00</updated>
<author>
<name>Yung-Ching LIN</name>
<email>yungching0725@gmail.com</email>
</author>
<published>2017-03-28T17:51:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fc9ade56e3eb451683a58089e32e79abb69e240e'/>
<id>fc9ade56e3eb451683a58089e32e79abb69e240e</id>
<content type='text'>
Change the PMIC bulk configuration from auto mode to sync mode to avoid the voltage shutdown issue

Signed-off-by: Ken Lin &lt;yungching0725@gmail.com&gt;
Acked-by: Akshay Bhat &lt;akshay.bhat@timesys.com&gt;
</content>
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<pre>
Change the PMIC bulk configuration from auto mode to sync mode to avoid the voltage shutdown issue

Signed-off-by: Ken Lin &lt;yungching0725@gmail.com&gt;
Acked-by: Akshay Bhat &lt;akshay.bhat@timesys.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>board: advantech: dms-ba16: Add the configuration options for display initialization</title>
<updated>2017-04-12T16:04:33+00:00</updated>
<author>
<name>Yung-Ching LIN</name>
<email>yungching0725@gmail.com</email>
</author>
<published>2017-03-28T17:51:22+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f6f7e73d4503f84723f699cd63ac18397db36858'/>
<id>f6f7e73d4503f84723f699cd63ac18397db36858</id>
<content type='text'>
Add the configuration options for display initialization in case we need to
do the display initialization in kernel to support different timing settings

Signed-off-by: Ken Lin &lt;yungching0725@gmail.com&gt;
Acked-by: Akshay Bhat &lt;akshay.bhat@timesys.com&gt;
</content>
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<pre>
Add the configuration options for display initialization in case we need to
do the display initialization in kernel to support different timing settings

Signed-off-by: Ken Lin &lt;yungching0725@gmail.com&gt;
Acked-by: Akshay Bhat &lt;akshay.bhat@timesys.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>treewide: replace #include &lt;asm/errno.h&gt; with &lt;linux/errno.h&gt;</title>
<updated>2016-09-23T21:55:42+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2016-09-21T02:28:55+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1221ce459d04a428f8880f58581f671b736c3c27'/>
<id>1221ce459d04a428f8880f58581f671b736c3c27</id>
<content type='text'>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap &lt;asm-generic/errno.h&gt;)

Replace all include directives for &lt;asm/errno.h&gt; with &lt;linux/errno.h&gt;.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
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<pre>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap &lt;asm-generic/errno.h&gt;)

Replace all include directives for &lt;asm/errno.h&gt; with &lt;linux/errno.h&gt;.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: imx: Add support for Advantech DMS-BA16 board</title>
<updated>2016-09-06T16:22:48+00:00</updated>
<author>
<name>Akshay Bhat</name>
<email>akshay.bhat@timesys.com</email>
</author>
<published>2016-07-29T15:44:46+00:00</published>
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<id>ff3832205eb53b3e0ceebb6cd5d8891e0ec455d9</id>
<content type='text'>
Add support for Advantech DMS-BA16 board. The board is based on Advantech
BA16 module which has a i.MX6D processor. The board supports:
 - FEC Ethernet
 - USB Ports
 - SDHC and MMC boot
 - SPI NOR
 - LVDS and HDMI display

Basic information about the module:
 - Module manufacturer: Advantech
 - CPU: Freescale ARM Cortex-A9 i.MX6D
 - SPECS:
     Up to 2GB Onboard DDR3 Memory;
     Up to 16GB Onboard eMMC NAND Flash
     Supports OpenGL ES 2.0 and OpenVG 1.1
     HDMI, 24-bit LVDS
     1x UART, 2x I2C, 8x GPIO,
     4x Host USB 2.0 port, 1x USB OTG port,
     1x micro SD (SDHC),1x SDIO, 1x SATA II,
     1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2

Signed-off-by: Akshay Bhat &lt;akshay.bhat@timesys.com&gt;
Cc: u-boot@lists.denx.de
Cc: sbabic@denx.de
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for Advantech DMS-BA16 board. The board is based on Advantech
BA16 module which has a i.MX6D processor. The board supports:
 - FEC Ethernet
 - USB Ports
 - SDHC and MMC boot
 - SPI NOR
 - LVDS and HDMI display

Basic information about the module:
 - Module manufacturer: Advantech
 - CPU: Freescale ARM Cortex-A9 i.MX6D
 - SPECS:
     Up to 2GB Onboard DDR3 Memory;
     Up to 16GB Onboard eMMC NAND Flash
     Supports OpenGL ES 2.0 and OpenVG 1.1
     HDMI, 24-bit LVDS
     1x UART, 2x I2C, 8x GPIO,
     4x Host USB 2.0 port, 1x USB OTG port,
     1x micro SD (SDHC),1x SDIO, 1x SATA II,
     1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2

Signed-off-by: Akshay Bhat &lt;akshay.bhat@timesys.com&gt;
Cc: u-boot@lists.denx.de
Cc: sbabic@denx.de
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: Add Advantech SOM-DB5800/SOM-6867 support</title>
<updated>2016-07-12T05:46:01+00:00</updated>
<author>
<name>George McCollister</name>
<email>george.mccollister@gmail.com</email>
</author>
<published>2016-06-21T17:07:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=215099a522dae18d4682964c6b850d12c45c98a0'/>
<id>215099a522dae18d4682964c6b850d12c45c98a0</id>
<content type='text'>
Add support for Advantech SOM-DB5800 with the SOM-6867 installed.
This is very similar to conga-qeval20-qa3-e3845 in that there is a
reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867)
installed.

Currently supported:
 - 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on
   SOM-DB5800.
 - 4x USB 2.0 (EHCI)
 - Video
 - SATA
 - Ethernet
 - PCIe
 - Realtek ALC892 HD Audio
   Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO
   HDA_SDI0 is set in DT to enable HD Audio codec.
   Pin defaults for codec pin complexs are not changed.

Not supported:
 - Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500)
 - USB 3.0 (XHCI)
 - TPM

Signed-off-by: George McCollister &lt;george.mccollister@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
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<pre>
Add support for Advantech SOM-DB5800 with the SOM-6867 installed.
This is very similar to conga-qeval20-qa3-e3845 in that there is a
reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867)
installed.

Currently supported:
 - 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on
   SOM-DB5800.
 - 4x USB 2.0 (EHCI)
 - Video
 - SATA
 - Ethernet
 - PCIe
 - Realtek ALC892 HD Audio
   Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO
   HDA_SDI0 is set in DT to enable HD Audio codec.
   Pin defaults for codec pin complexs are not changed.

Not supported:
 - Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500)
 - USB 3.0 (XHCI)
 - TPM

Signed-off-by: George McCollister &lt;george.mccollister@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
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</content>
</entry>
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