u-boot.git/board/altera, branch v2015.01

arm: socfpga: board: Repair Micrel PHY tuning

2014-12-16T14:32:14+00:00

Add proper error checking into the PHY tuning patch. Make the PHY tunning only
happen in case the KSZ9021 PHY is enabled in config. Call the config callback
after the tuning finished.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Tom Rini 
Cc: Pavel Machek

arm: socfpga: set skew settings for ethernet phy

2014-12-06T12:51:54+00:00

Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5
hardware.

Signed-off-by: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Pavel Machek 
Cc: Marek Vasut 
Cc: Tom Rini 
Cc: Albert Aribaud 
Cc: Wolfgang Denk

arm: socfpga: Add myself as maintainer for the SoCrates board

2014-12-06T12:51:54+00:00

Signed-off-by: Stefan Roese 
Cc: Marek Vasut 
Acked-by: Pavel Machek 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Masahiro Yamada

arm: socfpga: Add example UDC config

2014-11-07T15:32:02+00:00

Add example of an USB UDC configuration with DFU and UMS.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Vince Bridgers 
Acked-by: Pavel Machek 
Cc: Stefan Roese 
Reviewed-by: Lukasz Majewski

kconfig: arm: introduce symbol for ARM CPUs

2014-10-29T13:02:09+00:00

This commit introduces a Kconfig symbol for each ARM CPU:
CPU_ARM720T, CPU_ARM920T, CPU_ARM926EJS, CPU_ARM946ES, CPU_ARM1136,
CPU_ARM1176, CPU_V7, CPU_PXA, CPU_SA1100.
Also, it adds the CPU feature Kconfig symbol HAS_VBAR which is selected
for CPU_ARM1176 and CPU_V7.

For each target, the corresponding CPU is selected and the definition of
SYS_CPU in the corresponding Kconfig file is removed.

Also, it removes redundant "string" type in some Kconfig files.

Signed-off-by: Georges Savoundararadj 
Acked-by: Albert ARIBAUD 
Cc: Masahiro Yamada

arm: socfpga: Move cache_enable to CPU code

2014-10-06T15:46:51+00:00

Move icache_enable() and dcache_enable() function calls from
board code into the CPU code and into the enable_caches()
function. This is how the cache enabling code was designed
to work.

Signed-off-by: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Marek Vasut 
Cc: Tom Rini 
Cc: Albert Aribaud 
Cc: Wolfgang Denk 
Acked-by: Pavel Machek

arm: socfpga: cache: Enable D-Cache

2014-10-06T15:46:50+00:00

The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Albert Aribaud 
Cc: Tom Rini 
Cc: Wolfgang Denk 
Cc: Pavel Machek 
Acked-by: Pavel Machek

arm: socfpga: board: Align checkboard() output

2014-10-06T15:46:50+00:00

Cosmetic change to the checkboard() function output. Align the
output with the rest of initial output produced by U-Boot.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Albert Aribaud 
Cc: Tom Rini 
Cc: Wolfgang Denk 
Cc: Pavel Machek 
Acked-by: Pavel Machek

arm: socfpga: board: Correctly set ATAG position

2014-10-06T15:46:50+00:00

The bi_boot_params must point to offset 0x100 in DRAM. Make it so.

Signed-off-by: Pavel Machek 
Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Albert Aribaud 
Cc: Tom Rini 
Cc: Wolfgang Denk 
Cc: Pavel Machek

arm: socfpga: clock: Add missing stubs into board file

2014-10-06T15:46:48+00:00

Add some stub defines, which are used by the clock code, but are
missing from the auto-generated header file for the SoCFPGA family.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Albert Aribaud 
Cc: Tom Rini 
Cc: Wolfgang Denk 
Cc: Pavel Machek 
Acked-by: Dinh Nguyen 
Acked-by: Pavel Machek