u-boot.git/board/altera, branch v2015.04

arm: socfpga: Add Altera Arria V DK support

2015-03-04T22:07:04+00:00

Add support for the Altera Arria V development kit.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Stefan Roese 
Cc: Vince Bridgers

arm: socfpga: Zap board_early_init_f()

2015-03-04T22:07:04+00:00

Zap this unused empty function, no point in having it.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Acked-by: Dinh Nguyen 
Acked-by: Pavel Machek 
Reviewed-by: Stefan Roese 
Cc: Vince Bridgers

arm: socfpga: Zap checkboard()

2015-03-04T22:07:04+00:00

Since all boards now have a DT, instead of hard-coding the board
name into the U-Boot binary, read the board name from DT "model"
property.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Acked-by: Pavel Machek 
Acked-by: Stefan Roese 
Cc: Vince Bridgers

arm: socfpga: Drop cyclone5 suffix from board file name

2015-03-04T22:07:04+00:00

Drop the _cyclone5 suffix from socfpga_cyclone5.c since this file
will contain Arria 5 support as well.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Acked-by: Dinh Nguyen 
Acked-by: Pavel Machek 
Reviewed-by: Stefan Roese 
Cc: Vince Bridgers

arm: socfpga: Sync Cyclone V DK PLL configuration

2015-03-04T22:07:04+00:00

Sync SoCFPGA Cyclone V development kit pinmux configuration with
Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

NOTE: This change is useless until we get proper SPL support, at
      which point this will likely need further rework.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Acked-by: Dinh Nguyen 
Cc: Pavel Machek 
Reviewed-by: Stefan Roese 
Cc: Vince Bridgers

arm: socfpga: Sync Cyclone V DK pinmux configuration

2015-03-04T22:07:04+00:00

Sync SoCFPGA Cyclone V development kit pinmux configuration with
Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Acked-by: Dinh Nguyen 
Cc: Pavel Machek 
Reviewed-by: Stefan Roese 
Cc: Vince Bridgers

arm: socfpga: Minor coding style fix

2015-03-04T22:07:03+00:00

Replace multiple spaces with a single tab.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Acked-by: Dinh Nguyen 
Acked-by: Pavel Machek 
Reviewed-by: Stefan Roese 
Cc: Vince Bridgers

arm: socfpga: board: Repair Micrel PHY tuning

2014-12-16T14:32:14+00:00

Add proper error checking into the PHY tuning patch. Make the PHY tunning only
happen in case the KSZ9021 PHY is enabled in config. Call the config callback
after the tuning finished.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Tom Rini 
Cc: Pavel Machek

arm: socfpga: set skew settings for ethernet phy

2014-12-06T12:51:54+00:00

Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5
hardware.

Signed-off-by: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Pavel Machek 
Cc: Marek Vasut 
Cc: Tom Rini 
Cc: Albert Aribaud 
Cc: Wolfgang Denk

arm: socfpga: Add myself as maintainer for the SoCrates board

2014-12-06T12:51:54+00:00

Signed-off-by: Stefan Roese 
Cc: Marek Vasut 
Acked-by: Pavel Machek 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Masahiro Yamada