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<title>u-boot.git/board/altera, branch v2015.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board/altera?h=v2015.10</id>
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<updated>2015-09-23T01:55:28Z</updated>
<entry>
<title>arm: socfpga: update MAINTAINERS' file for cyclone5_socdk and arria5_socdk</title>
<updated>2015-09-23T01:55:28Z</updated>
<author>
<name>Dinh Nguyen</name>
<email>dinguyen@opensource.altera.com</email>
</author>
<published>2015-09-22T22:01:33Z</published>
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<id>urn:sha1:4348f36bbbc91633022a39739c584a83af1762d8</id>
<content type='text'>
commit "arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files"
renames the configs files, so we should update the MAINTAINERS' entry. At
the same time, update the email for Dinh Nguyen.

Signed-off-by: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: Fix ArriaV SoCDK PLL config</title>
<updated>2015-08-23T09:56:21Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2015-08-19T05:46:49Z</published>
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<id>urn:sha1:29aa439759ed2e5dfa45cd8d6d5a1d51604e3820</id>
<content type='text'>
Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: Fix MAINTAINERS entry for CV/AV SoCDK</title>
<updated>2015-08-23T09:56:20Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2015-08-19T20:25:44Z</published>
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<id>urn:sha1:d418301167a1b8ccc64060a5a538c2980cdae073</id>
<content type='text'>
Repair the maintainer entries so they match the current state of code.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: Make the pinmux table const u8</title>
<updated>2015-08-23T09:56:20Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2015-08-10T20:17:46Z</published>
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<id>urn:sha1:cc9429a5562489cf8a4eb0d722c36e1bdfde4907</id>
<content type='text'>
Now that we're actually converting the QTS-generated header files,
we can even adjust their data types. A good candidate for this is
the pinmux table, where each entry can have value in the range of
0..3, but each element is declared as unsigned long. By changing
the type to u8, we can save over 600 Bytes from the SPL, so do it.
This patch also constifies the array.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: Switch to filtered QTS files</title>
<updated>2015-08-23T09:56:20Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2015-08-10T19:21:07Z</published>
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<id>urn:sha1:f6badb0d89ae1221c8aa83138632613f91a48715</id>
<content type='text'>
Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: Remove AV-specific parts from CV-SoCDK</title>
<updated>2015-08-23T09:56:20Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2015-08-10T19:39:52Z</published>
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<id>urn:sha1:37b3a30ae692c9feb92257bb82838642f4c894eb</id>
<content type='text'>
Just remove the ArriaV specific parts from the CycloneV SoCDK board
and they are no longer needed now.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: Remove CV-specific parts from AV-SoCDK</title>
<updated>2015-08-23T09:56:20Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2015-08-10T19:37:14Z</published>
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<id>urn:sha1:c68eea0492e68e29ccdca5ac2b88c90899c4d80d</id>
<content type='text'>
Just remove the CycloneV specific parts from the ArriaV SoCDK board
and they are no longer needed now.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: Split Altera socfpga into AV and CV SoCDK</title>
<updated>2015-08-23T09:56:19Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2015-08-10T19:24:53Z</published>
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<id>urn:sha1:f089240128329fe6a49a5272aef732b47613c2f5</id>
<content type='text'>
The board/altera/socfpga directory is not a generic SoCFPGA machine
anymore, but instead it represents the Altera SoCDK board. To make
matters more complicated, it represents both CycloneV and ArriaV
variant.

On the other hand, nowadays, the content of this board directory is
mostly comprised of QTS-generated header files, while all the generic
code is in arch/arm/mach-socfpga already.

Thus, this patch splits the board/altera/socfpga into a separate
board directory for ArriaV SoCDK and CycloneV SoCDK, so that each
can be populated with the correct QTS-generated header files for
that particular board.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: Move wrappers into platform directory</title>
<updated>2015-08-23T09:56:19Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2015-08-02T19:12:09Z</published>
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<id>urn:sha1:ca62d2e1fca4e89b1e15e6bdc634f6ef39a7360d</id>
<content type='text'>
Move the wrappers for QTS-generated files into platform directory
out of the board directory. The trick here is to add -I to CFLAGS
such that it points to the board directory in source tree and thus
the qts/ directory there is still reachable.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>ddr: altera: sequencer: add RW_MGR_MEM_NUMBER_OF_RANKS</title>
<updated>2015-08-08T12:14:30Z</updated>
<author>
<name>Dinh Nguyen</name>
<email>dinguyen@opensource.altera.com</email>
</author>
<published>2015-08-05T03:12:32Z</published>
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<id>urn:sha1:cf96848bc76c7d680100e914b088ca34ed4e04e0</id>
<content type='text'>
Fix build error for socfpga_cyclone5_defconfig:

board/altera/socfpga/wrap_sdram_config.c:245:26: error: ‘RW_MGR_MEM_NUMBER_OF_RANKS’ undeclared here (not in a function)
make[2]: *** [spl/board/altera/socfpga/wrap_sdram_config.o] Error 1

Signed-off-by: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
</content>
</entry>
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