u-boot.git/board/amcc/sequoia/init.S, branch v2009.01

rename CFG_ macros to CONFIG_SYS

2008-10-18T19:54:03Z

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD

ppc4xx: Sequoia coding style cleanup and beautification

2008-01-16T10:24:28Z

Signed-off-by: Matthias Fuchs

ppc4xx: Make Sequoia boot vxWorks

2008-01-10T18:06:54Z

vxWorks expects in TLB 0 a entry for the Machine Check interrupt TLB 1 a entry for the RAM TLB 2 a entry for the EBC TLB 3 a entry for the boot flash After changing the baudrate to 9600 I had no problems to boot the vxWorks image as distributed by WindRiver (Revision 2.0/1 from June 18, 2007) Signed-off-by: Niklaus Giger

Use definitions from "asm-ppc/mmu.h" in init.S for Sequoia

2007-12-27T18:35:35Z

Signed-off-by: Larry Johnson

ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAM

2007-10-31T20:21:47Z

This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files and to the Sequoia TLB init code. Now the cache can be enabled on 44x boards by defining CONFIG_4xx_DCACHE in the board config file. This option will disappear, when more boards use is successfully and no more known problems exist. This is tested successfully on Sequoia and Katmai. The only problem that needs to be fixed is, that USB is not working on Sequoia right now, since it will need some cache handling code too, similar to the 4xx EMAC driver. Signed-off-by: Stefan Roese

ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia

2007-08-31T13:21:46Z

The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese . o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese . o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn Signed-off-by: Stefan Roese

[PATCH] Add DDR2 optimization code for Sequoia (440EPx) board

2007-01-05T09:38:05Z

This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese

Add support for AMCC Sequoia PPC440EPx eval board

2006-09-07T09:51:23Z

- Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006