u-boot.git/board/amcc, branch v1.3.0

ppc4xx: Add 667/133 (CPU/PLB) frequency setup to Sequoia bootstrap command

2007-10-18T05:44:56Z

Signed-off-by: Stefan Roese

ppc4xx: Fix bug in I2C bootstrap values for Sequoia/Rainier

2007-10-15T09:39:00Z

The I2C bootstrap values that can be setup via the "bootstrap" command, were setup incorrect regarding the generation of the internal sync PCI clock. The values for PLB clock == 133MHz were slighly incorrect and the values for PLB clock == 166MHz were totally incorrect. This could lead to a hangup upon booting while PCI configuration scan. This patch fixes this issue and configures valid PCI divisor values for the sync PCI clock, with respect to the provided external async PCI frequency. Here the values of the formula in the chapter 14.2 "PCI clocking" from the 440EPx users manual: AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz 33MHz async PCI frequency: PLB = 133: => 32 <= 44.3 <= 65 (div = 3) PLB = 166: => 32 <= 55.3 <= 65 (div = 3) 66MHz async PCI frequency: PLB = 133: => 65 <= 66.5 <= 132 (div = 2) PLB = 166: => 65 <= 83 <= 132 (div = 2) Signed-off-by: Stefan Roese

ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & Yosemite

2007-10-15T09:29:33Z

The BCSR status bit for the 66MHz PCI operation was correctly addressed (MSB/LSB problem). Now the correct currently setup PCI frequency is displayed upon bootup. This patch also fixes this problem on Rainier & Yellowstone, since these boards use the same souce code as Sequoia & Yosemite do. Signed-off-by: Stefan Roese

ppc4xx: Coding style cleanup

2007-10-02T09:44:46Z

Signed-off-by: Stefan Roese

Program EPLD to force full duplex mode for PHY.

2007-10-02T09:30:37Z

EPLD forces modes of PHY operation. By default full duplex is turned off. This fix turns it on. Signed-off-by: Grzegorz Bernacki

Fix cases where DECLARE_GLOBAL_DATA_PTR was not declared as global

2007-09-15T18:48:41Z

Signed-off-by: Wolfgang Denk

[PPC440SPe] PCIe environment settings for Katmai and Yucca

2007-09-07T16:35:37Z

- 'pciconfighost' is set by default in order to be able to scan bridges behind the primary host/PCIe - 'pciscandelay' env variable is recognized to allow for user-controlled delay before the PCIe bus enumeration; some peripheral devices require a significant delay before they can be scanned (e.g. LSI8408E); without the delay they are not detected Signed-off-by: Grzegorz Bernacki

[PPC440SPe] Improve PCIe configuration space access

2007-09-07T16:20:23Z

- correct configuration space mapping - correct bus numbering - better access to config space Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the first device on the first bus. We now allow to configure up to 16 buses; also, scanning for devices behind the PCIe-PCIe bridge is supported, so peripheral devices farther in hierarchy can be identified. Signed-off-by: Grzegorz Bernacki

ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia

2007-08-31T13:21:46Z

The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese . o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese . o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn Signed-off-by: Stefan Roese

ppc4xx: Update Sequoia/Rainier bootstrap command

2007-08-16T07:52:29Z

As suggested by David Mitchell, here an update for the Sequoia/Rainier bootstrap command. Signed-off-by: Stefan Roese