u-boot.git/board/amcc, branch v2009.03

Fix AMCC Sequoia board DDR memory configuration

2009-03-17T09:52:36+00:00

Sequoia board schematics (DES0211_11_SCH_11.pdf, page 5, unit U1D)
specifies that BankSel#1 is not connected, while bootloader memory
configuration is (board/amcc/sequoia/sdram.c):
       mtsdram(DDR0_10, 0x00000300);
i.e. both Chip Selects used - not correct.

If we change to correct value here:
       mtsdram(DDR0_10, 0x00000100);
memory is accessible OK also.

Signed-off-by: Mikhail Zolotaryov 
Signed-off-by: Stefan Roese

ppc4xx: Fix problem with board_eth_init() vs cpu_eth_init() on AMCC boards

2009-02-12T05:08:07+00:00

Some AMCC eval boards do have a board_eth_init() function calling
pci_eth_init(). These boards need to call cpu_eth_init() explicitly now
with the new eth_init rework.

Signed-off-by: Stefan Roese

Command usage cleanup

2009-01-28T07:49:52+00:00

Remove command name from all command "usage" fields and update
common/command.c to display "name - usage" instead of
just "usage". Also remove newlines from command usage fields.

Signed-off-by: Peter Tyser

amcc: Clean up command usage output

2009-01-28T07:43:52+00:00

Update taihu and taishan commands to use cmd_usage() function
to display usage messages.

Signed-off-by: Peter Tyser

Standardize command usage messages with cmd_usage()

2009-01-28T07:43:45+00:00

Signed-off-by: Peter Tyser

ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initialization

2008-11-21T10:02:04+00:00

Expanded OCM TLB to allow access to 64K OCM as well as 256K of
internal SRAM.

Adjusted internal SRAM initialization to match updated user
manual recommendation.

OCM & ISRAM are now mapped as follows:
        physical        virtual         size
ISRAM   0x4_0000_0000   0xE300_0000     256k
OCM     0x4_0004_0000   0xE304_0000     64k

A single TLB was used for this mapping.

Signed-off-by: Dave Mitchell 
Signed-off-by: Stefan Roese

ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRs

2008-11-21T09:52:33+00:00

Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and
L2 cache DCRs from ppc440.h to this new header.

Also converted these DCR defines from lowercase to uppercase and
modified referencing modules to use them.

Signed-off-by: Dave Mitchell 
Signed-off-by: Stefan Roese

Align end of bss by 4 bytes

2008-11-18T22:13:16+00:00

Most of the bss initialization loop increments 4 bytes
at a time. And the loop end is checked for an 'equal'
condition. Make the bss end address aligned by 4, so
that the loop will end as expected.

Signed-off-by: Selvamuthukumar 
Signed-off-by: Wolfgang Denk

Coding Style cleanup, update CHANGELOG

2008-11-02T15:14:22+00:00

Signed-off-by: Wolfgang Denk

Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

2008-10-21T19:19:35+00:00