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<title>u-boot.git/board/bitmain, branch next</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>board: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD</title>
<updated>2024-10-11T17:44:48+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-09-30T01:49:47+00:00</published>
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<id>dac3ce976a9b06be5aadbd857c4b64a8c521c6d4</id>
<content type='text'>
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>xilinx: Introduce board_late_init_xilinx()</title>
<updated>2020-04-27T11:57:17+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2020-03-31T10:39:37+00:00</published>
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<id>80fdef12b22ab70f9d83343016abcd3b50a87d7c</id>
<content type='text'>
This function should keep common shared late configurations for Xilinx
SoCs.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This function should keep common shared late configurations for Xilinx
SoCs.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: zynq: Add support for Bitmain Antminer S9 control board</title>
<updated>2018-05-31T11:50:39+00:00</updated>
<author>
<name>Ezequiel Garcia</name>
<email>ezequiel@vanguardiasur.com.ar</email>
</author>
<published>2018-01-12T15:33:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c66f5620e6a63b1912c017781c7eec6400dde292'/>
<id>c66f5620e6a63b1912c017781c7eec6400dde292</id>
<content type='text'>
This is control board on Bitmain Antminer S9.
There are 3 board variables with 256MB, 512MB and 1024MB DDR.
DDR memory is automatically detected with using get_with using
get_ram_size().

Bitmain is using 16MB space for FPGA which is handled via
reserved-memory. Also U-Boot is allocating 16B for storing bootcounts.
Watchdog is started but never service in U-Boot.

SPL MMC is working. SPL NAND is not working because it is not supported
as of now.

Signed-off-by: Ezequiel Garcia &lt;ezequiel@vanguardiasur.com.ar&gt;
Signed-off-by: Michal Simek &lt;monstr@monstr.eu&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
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<pre>
This is control board on Bitmain Antminer S9.
There are 3 board variables with 256MB, 512MB and 1024MB DDR.
DDR memory is automatically detected with using get_with using
get_ram_size().

Bitmain is using 16MB space for FPGA which is handled via
reserved-memory. Also U-Boot is allocating 16B for storing bootcounts.
Watchdog is started but never service in U-Boot.

SPL MMC is working. SPL NAND is not working because it is not supported
as of now.

Signed-off-by: Ezequiel Garcia &lt;ezequiel@vanguardiasur.com.ar&gt;
Signed-off-by: Michal Simek &lt;monstr@monstr.eu&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
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</content>
</entry>
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