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<title>u-boot.git/board/cds, branch v1.3.0</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board/cds?h=v1.3.0</id>
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<updated>2007-10-19T16:25:01Z</updated>
<entry>
<title>Improve handling of PCI interrupt device tree fixup on MPC85xx CDS</title>
<updated>2007-10-19T16:25:01Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2007-10-11T05:29:18Z</published>
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<id>urn:sha1:7600d47b8f6a10019e537dc9a62aa1498df58d25</id>
<content type='text'>
On the MPC85xx CDS we have two issues:

1. The device tree fixup code did not check to see if the property we are
trying to update is actually found.  Its possible that it would update
random memory starting at 0.

2. Newer Linux kernel's have moved the location of the PCI nodes to be
sibilings of the soc node and not children.  The explicit PATH to the PCI
node would not be found for these device trees.  Add the ability to handle
both paths.  In the future we shouldn't handle such fixups by explicit path.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>ft_board_setup update 85xx/86xx of pci/pcie bus-range property.</title>
<updated>2007-09-04T21:00:41Z</updated>
<author>
<name>Ed Swarthout</name>
<email>Ed.Swarthout@freescale.com</email>
</author>
<published>2007-08-30T06:58:48Z</published>
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<id>urn:sha1:f75e89e9b5714db2b0e80074071dfbdd6f59488a</id>
<content type='text'>
pcie is now differentiated from pci.  Add 8641 bus-range updates.

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
</content>
</entry>
<entry>
<title>8548cds fixes</title>
<updated>2007-08-29T05:11:59Z</updated>
<author>
<name>Ed Swarthout</name>
<email>Ed.Swarthout@freescale.com</email>
</author>
<published>2007-08-21T14:38:59Z</published>
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<id>urn:sha1:4bf4abb8a4e9955556b120a1aafa30c03e74032a</id>
<content type='text'>
Restore CONFIG_EXTRA_ENV_SETTINGS definition which contains the
correct consoledev needed for linux boot.
Standardize on fdt{file,addr} var to hold dtb file name.

Set PCI inbound memory region from CFG_MEMORY_{BUS,PHYS}.

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
</content>
</entry>
<entry>
<title>85xxCDS: Add make targets for legacy systems.</title>
<updated>2007-08-14T06:51:39Z</updated>
<author>
<name>Randy Vinson</name>
<email>rvinson@linuxbox.(none)</email>
</author>
<published>2007-02-28T02:42:22Z</published>
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<id>urn:sha1:7f3f2bd2dc08e0b05e185662ca2e2d283757104a</id>
<content type='text'>
The PCI ID select values on the Arcadia main board differ depending
on the version of the hardware. The standard configuration supports
Rev 3.1. The legacy target supports Rev 2.x.

Signed-off-by Randy Vinson &lt;rvinson@mvista.com&gt;
</content>
</entry>
<entry>
<title>85xxCDS: Enable the VIA PCI-to-ISA bridge.</title>
<updated>2007-08-14T06:50:09Z</updated>
<author>
<name>Andy Fleming</name>
<email>afleming@freescale.com</email>
</author>
<published>2007-08-14T06:50:09Z</published>
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<id>urn:sha1:e41094c7e38177c755fbd9b182018069614f080d</id>
<content type='text'>
Author: Randy Vinson &lt;rvinson@linuxbox.(none)&gt;

Enable the PCI-to-ISA bridge in the VIA Southbridge located on the
Arcadia main board.

Signed-off-by: Randy Vinson &lt;rvinson@mvista.com&gt;
Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>8548cds PCIE support.</title>
<updated>2007-08-14T06:39:00Z</updated>
<author>
<name>Ed Swarthout</name>
<email>Ed.Swarthout@freescale.com</email>
</author>
<published>2007-07-27T06:50:52Z</published>
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<id>urn:sha1:f2cff6b104f82b993bef6086ce0c97159bbe1add</id>
<content type='text'>
Make the early L1 cache stack region guarded to prevent speculative
fetches outside the locked range.

Use _PHYS defines, not _MEM for cpu-side PCI memory mapped regions.
init.S whitespace cleanup.

Allow TEXT_BASE value to be specified on command line.  This allows it
to be set to 0xfffc0000 which cuts the uboot binary in half.

Clear and enable lbc and ecm errors.

Update last_busno in device-tree for pci and pcie.

Remove load of obsolete cpu/mpc85xx/pci.0

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx</title>
<updated>2007-05-16T22:07:21Z</updated>
<author>
<name>Kim Phillips</name>
<email>kim.phillips@freescale.com</email>
</author>
<published>2007-05-16T21:52:19Z</published>
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<id>urn:sha1:255a3577c848706441daee0174543efe205a77f8</id>
<content type='text'>
For all practical u-boot purposes, TSECs don't differ throughout the
mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx.

Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</content>
</entry>
<entry>
<title>Cleaned up some 85xx PCI bugs</title>
<updated>2007-05-02T20:50:13Z</updated>
<author>
<name>Andy Fleming</name>
<email>afleming@freescale.com</email>
</author>
<published>2007-02-24T07:08:13Z</published>
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<id>urn:sha1:ffa621a0d12a1ccd81c936c567f8917a213787a8</id>
<content type='text'>
* Cleaned up the CDS PCI Config Tables and added NULL entries to
  the end
* Fixed PCIe LAWBAR assignemt to use the cpu-relative address
* Fixed 85xx PCI code to assign powar region sizes based on the
  config values (rather than hard-coding them)
* Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>Changed BOOKE_PAGESZ_nGB to BOOKE_PAGESZ_nG</title>
<updated>2007-04-24T00:58:28Z</updated>
<author>
<name>Andy Fleming</name>
<email>afleming@freescale.com</email>
</author>
<published>2007-02-23T23:11:16Z</published>
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<id>urn:sha1:45cef612cc601d2d1c890fbbd7cdc9609a189a46</id>
<content type='text'>
The other pagesz constants use one letter to specify order of
magnitude.  Also change the one reference to it in mpc8548cds/init.S

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>u-boot: Fix the 85xxcds tsec bug</title>
<updated>2007-04-24T00:58:27Z</updated>
<author>
<name>Zang Roy-r61911</name>
<email>tie-fei.zang@freescale.com</email>
</author>
<published>2006-12-18T09:01:04Z</published>
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<id>urn:sha1:0b1934ba12fd408fcc3b8bd9f4b04864c42a42bf</id>
<content type='text'>
Fix the 85xxcds tsec bug.
When enable PCI, tsec.o should be added to u-boot.lds to make tsec work.

Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
</content>
</entry>
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