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<title>u-boot.git/board/compulab/trimslice/trimslice.c, branch v2016.05</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board/compulab/trimslice/trimslice.c?h=v2016.05</id>
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<updated>2016-01-12T17:19:09Z</updated>
<entry>
<title>dm: tegra: net: Convert tegra boards to driver model for Ethernet</title>
<updated>2016-01-12T17:19:09Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-11-29T20:18:01Z</published>
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<id>urn:sha1:96350f729c4244bae879c39449ef5d6caf553e62</id>
<content type='text'>
Adjust all Tegra boards to use driver model for Ethernet, now that the
required drivers are converted.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Enable PCIe on TrimSlice</title>
<updated>2014-12-18T20:19:20Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-10T05:25:14Z</published>
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<id>urn:sha1:7dd8738f08144b01d91185f250af9ce2648cb25f</id>
<content type='text'>
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network driver so that the device can boot over
the network.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Tegra20 pinmux cleanup</title>
<updated>2014-04-17T15:41:05Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2014-03-21T18:28:58Z</published>
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<id>urn:sha1:70ad375ee444645001d3ca78bb17790b50232999</id>
<content type='text'>
This renames all the Tegra20 pinmux pins and functions so they have a
prefix which matches the type name.

The entries in tegra20_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Add GPL-2.0+ SPDX-License-Identifier to source files</title>
<updated>2013-07-24T13:44:38Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2013-07-08T07:37:19Z</published>
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<id>urn:sha1:1a4596601fd395f3afb8f82f3f840c5e00bdd57a</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>Tegra: MMC: Add DT support to MMC driver for all T20 boards</title>
<updated>2013-03-14T18:06:42Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren.nvidia@gmail.com</email>
</author>
<published>2013-02-21T12:31:30Z</published>
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<id>urn:sha1:c9aa831ee26f629fbd2df67cab8bb357777e2256</id>
<content type='text'>
tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc.
Tested on Seaboard, fully functional.

Tamonten boards (medcom-wide, plutux, and tec) use a different/new
dtsi file w/common settings.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: TrimSlice: add support for USB1 port</title>
<updated>2012-11-19T15:15:41Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2012-11-01T12:14:37Z</published>
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<id>urn:sha1:7155dc97f62a7bb3c64eee0a643c8e329abe9f3c</id>
<content type='text'>
TrimSlice's USB1 port has two purposes; it either acts as a device port
hosting Tegra's USB recovery protocol, or acts as a host port connected
to the internal USB-&gt;SATA bridge chip, which may in turn be connected to
an SSD or HDD. Add the appropriate device tree and board configuration
options to enable this port as a host port, and route the port to the
SATA bridge using the VBUS GPIO.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra20: rework UART GPIO handling</title>
<updated>2012-10-15T18:54:07Z</updated>
<author>
<name>Lucas Stach</name>
<email>dev@lynxeye.de</email>
</author>
<published>2012-09-25T20:21:14Z</published>
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<id>urn:sha1:0cd10c7abf3d210c921a0e5c86c2abdbf98c68c5</id>
<content type='text'>
Rename board provided gpio_config_uart() to
gpio_early_init_uart() as it does the same thing as the equally
called function provided by the uart-switch code. This allows
to simply call this function in early board init whether or not
we are building with CONFIG_UART_SWITCH defined.

Also provide a weak symbol for this function, to avoid the
need to provide this function for boards that don't need any
fixup.

This patch supersedes the earlier posted
"tegra: convert gpio_config_uart to weak symbol".
Build tested with MAKEALL -s tegra20

Signed-off-by: Lucas Stach &lt;dev@lynxeye.de&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Tegra20: Move some include files to arch-tegra for sharing with Tegra30</title>
<updated>2012-10-15T18:54:06Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2012-09-19T22:50:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=150c24936b70ce36e11069038ba8e955704cab3a'/>
<id>urn:sha1:150c24936b70ce36e11069038ba8e955704cab3a</id>
<content type='text'>
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h.
Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines &amp; structs
that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20'
'root' file.

All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Tegra: Change Tegra20 to Tegra in common code, prep for T30</title>
<updated>2012-09-10T20:01:24Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2012-09-05T00:00:24Z</published>
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<id>urn:sha1:29f3e3f24832fccdd7ce5fa961bc4d4005b07381</id>
<content type='text'>
Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate.
Convert tegra20_ source file and function names to tegra_, also.

Upcoming Tegra30 port will use common code/defines/names where possible.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra20: rename tegra2 -&gt; tegra20</title>
<updated>2012-09-01T12:58:21Z</updated>
<author>
<name>Allen Martin</name>
<email>amartin@nvidia.com</email>
</author>
<published>2012-08-31T08:30:00Z</published>
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<id>urn:sha1:00a2749d7be5b0e6cb6435187ec8fea600b44627</id>
<content type='text'>
This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.

Signed-off-by: Allen Martin &lt;amartin@nvidia.com&gt;
Acked-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Tested-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
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