u-boot.git/board/data_modul, branch v2024.01

ARM: imx: Update DRAM timings with inline ECC on Data Modul i.MX8M Plus eDM SBC

2023-12-14T18:29:08Z

Import DRAM timings generated by the DDR tool 3.31 which introduce assorted tweaks to the DRAM controller settings. Furthermore, enable DBI to improve noise resilience of the DRAM bus by reducing the number of bit changes on the bus. Reduce the DRAM rate to 3600 MTps to remove all remaining correctable errors reported by EDAC . It is not entirely clear why the slightly faster setting does produce sporadic correctable errors, while this one does not, but this could be related to simpler PLL setting at 3600 MTps. Enable inline ECC which is necessary to detect ECC errors and collect statistics by the EDAC driver in Linux. This reduces the DRAM size by 64 MiB for each 512 MiB of DRAM, so for a 4 GiB device the available DRAM size becomes 3.5 GiB . Signed-off-by: Marek Vasut Reviewed-by: Fabio Estevam

ARM: imx: Force DRAM regulators into FPWM mode on Data Modul i.MX8M Plus eDM SBC

2023-12-14T18:29:08Z

In case the Buck5 and Buck6 regulators which supply DRAM Vdd1 and Vdd2/Vddq respectively operate in automatic PWM/PFM mode, the DRAM EDAC detects more correctable errors than if the regulators operate in forced PWM only mode. Force DRAM regulators to forced PWM mode only to stop tempting the DRAM. Signed-off-by: Marek Vasut Reviewed-by: Fabio Estevam

spl: mmc: Introduce proper layering for spl_mmc_get_uboot_raw_sector()

2023-10-17T21:55:10Z

Introduce two new weak functions, arch_spl_mmc_get_uboot_raw_sector() and board_spl_mmc_get_uboot_raw_sector(), each of which can be overridden at a matching level, that is arch/ and board/ , in addition to the existing weak function spl_mmc_get_uboot_raw_sector(). This way, architecture code can define a default architecture specific implementation of arch_spl_mmc_get_uboot_raw_sector(), while the board code can override that using board_spl_mmc_get_uboot_raw_sector() which takes precedence over the architecture code. In some sort of unlikely special case where code has to take precedence over board code too, the spl_mmc_get_uboot_raw_sector() is still left out to be a weak function, but it should be unlikely that this is ever needed to be overridden. Signed-off-by: Marek Vasut

MAINTAINERS: Fix path typos and similar

2023-07-25T16:44:47Z

We have a number of cases where the in-tree path of files and where they presumably were when the first version of a patch were posted differ slightly. Correct these to point at where the files are now. Signed-off-by: Tom Rini Reviewed-by: Simon Glass

ARM: dts: imx: Fix eMMC boot on Data Modul i.MX8M Plus eDM SBC

2023-07-13T09:29:40Z

In case the i.MX8M Plus starts from eMMC BOOT1/BOOT2 HW partitions, the flash.bin container is stored at offset 0 from the start, that means the fitImage itb is at offset 0x2c0 instead of 0x300 sectors from the start. Handle this difference in custom spl_mmc_get_uboot_raw_sector() . Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Reviewed-by: Jaehoon Chung

ARM: dts: imx: Add support for Data Modul i.MX8M Plus eDM SBC

2023-04-04T07:35:39Z

Add support for Data Modul i.MX8M Plus eDM SBC board. This is an evaluation board for various custom display units. Currently supported are serial console, ethernet, eMMC, SD, SPI NOR, USB. Signed-off-by: Marek Vasut

ARM: imx: Factor common code out of Data Modul i.MX8M Mini eDM SBC

2023-01-30T22:23:02Z

Pull common.c into common subdirectory of the board file, since this code can be reused by other Data Modul SBCs. Drop the include of lpddr4_timing.h, which is unneeded. Signed-off-by: Marek Vasut

ARM: imx: Drop board side icache enable on Data Modul i.MX8M Mini eDM SBC

2023-01-30T22:23:01Z

The icache is enabled in common architecture code since commit: 2fa763baa1c ("ARM: imx: Enable instruction cache early on on i.MX8M") Drop the board side duplicate code. Signed-off-by: Marek Vasut

ARM: imx: Deduplicate i.MX8M SNVS LPGPR unlock

2022-09-20T16:30:02Z

Pull this LPGPR unlock into common code, since it is used in multiple systems already. Signed-off-by: Marek Vasut

ARM: imx: Update Data Modul i.MX8M Mini eDM SBC DRAM timing

2022-09-18T20:56:10Z

Adjust the DRAM timing settings for this board per ones provided by hardware department. The change is applied to the LPDDR4 MR11 register CA ODT configuration, from RZQ/6 to RZQ/3, which fixes stability issues on subset of boards. The DDR PHY PIE block has been updated accordingly. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Reviewed-by: Fabio Estevam