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<title>u-boot.git/board/emulation, branch v2020.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>common: Move some board functions out of common.h</title>
<updated>2019-12-02T23:25:21+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-11-14T19:57:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5255932f0167c502fc7fce527bfe7e81df3322f9'/>
<id>5255932f0167c502fc7fce527bfe7e81df3322f9</id>
<content type='text'>
A number of board function belong in init.h with the others. Move them.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
A number of board function belong in init.h with the others. Move them.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: qemu: Fix kconfig build warning</title>
<updated>2019-08-26T08:09:02+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2019-08-08T06:04:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=44016bc59870c8816fe2cd4721dc5ff11038dd98'/>
<id>44016bc59870c8816fe2cd4721dc5ff11038dd98</id>
<content type='text'>
When 'make qemu-riscv64_defconfig', there is a build warning:

  board/emulation/qemu-riscv/Kconfig:24:
  warning: config symbol defined without type

Fix it by specifying the config symbol type to 'hex'.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
</content>
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<pre>
When 'make qemu-riscv64_defconfig', there is a build warning:

  board/emulation/qemu-riscv/Kconfig:24:
  warning: config symbol defined without type

Fix it by specifying the config symbol type to 'hex'.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: qemu: add SPL configuration</title>
<updated>2019-08-26T08:07:42+00:00</updated>
<author>
<name>Lukas Auer</name>
<email>lukas.auer@aisec.fraunhofer.de</email>
</author>
<published>2019-08-21T19:14:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e456a81935aafcecc8e53a7cd35efe9267781041'/>
<id>e456a81935aafcecc8e53a7cd35efe9267781041</id>
<content type='text'>
Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL
enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The
configurations are meant to help the development of SPL on RISC-V.

The configurations enable RAM as the only SPL boot device. Images must
be loaded at address 0x80200000. In the default boot flow, U-Boot SPL
starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot
proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is
then started in supervisor mode by OpenSBI.

Signed-off-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
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<pre>
Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL
enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The
configurations are meant to help the development of SPL on RISC-V.

The configurations enable RAM as the only SPL boot device. Images must
be loaded at address 0x80200000. In the default boot flow, U-Boot SPL
starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot
proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is
then started in supervisor mode by OpenSBI.

Signed-off-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>env: Move env_set_hex() to env.h</title>
<updated>2019-08-11T20:43:41+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-08-01T15:46:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c7694dd4837ba12db3bcda872a1047a44566e0e8'/>
<id>c7694dd4837ba12db3bcda872a1047a44566e0e8</id>
<content type='text'>
Move env_set_hex() over to the new header file along with env_set_addr()
which uses it.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
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<pre>
Move env_set_hex() over to the new header file along with env_set_addr()
which uses it.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>qemu-riscv: enable VIRTIO_PCI</title>
<updated>2019-07-18T15:31:28+00:00</updated>
<author>
<name>David Abdurachmanov</name>
<email>david.abdurachmanov@gmail.com</email>
</author>
<published>2019-07-03T12:50:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1493b140e4a9211635964cd1c0276e599405f403'/>
<id>1493b140e4a9211635964cd1c0276e599405f403</id>
<content type='text'>
libvirt v.5.3.0 with QEMU 4.0.0 or above uses PCI automatically and
thus devices (network, storage, etc) are connected via PCI.

Signed-off-by: David Abdurachmanov &lt;david.abdurachmanov@sifive.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
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<pre>
libvirt v.5.3.0 with QEMU 4.0.0 or above uses PCI automatically and
thus devices (network, storage, etc) are connected via PCI.

Signed-off-by: David Abdurachmanov &lt;david.abdurachmanov@sifive.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: qemu: Enable e1000 and nvme support</title>
<updated>2019-06-05T05:19:15+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2019-05-15T15:42:59+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e64db0d92e320beec3214b78a4fb5cb81b8652dc'/>
<id>e64db0d92e320beec3214b78a4fb5cb81b8652dc</id>
<content type='text'>
Since we have added the PCI support to the 'virt' target, enable
e1000 and NVME as alternate network and storage devices for these
virtio based devices.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Tested-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Since we have added the PCI support to the 'virt' target, enable
e1000 and NVME as alternate network and storage devices for these
virtio based devices.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Tested-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: qemu: Enable PCI host ECAM generic driver</title>
<updated>2019-06-05T05:19:15+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2019-05-15T15:42:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cd6b6199eab1229547ac896f916b7735f77fa554'/>
<id>cd6b6199eab1229547ac896f916b7735f77fa554</id>
<content type='text'>
QEMU 4.0.0 'virt' target integrates a generic ECAM PCI host.
Enable the driver for it.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Tested-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
QEMU 4.0.0 'virt' target integrates a generic ECAM PCI host.
Enable the driver for it.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Tested-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: qemu: Use correct SYS_TEXT_BASE for S-mode on 32bit system</title>
<updated>2019-05-09T08:46:24+00:00</updated>
<author>
<name>Anup Patel</name>
<email>Anup.Patel@wdc.com</email>
</author>
<published>2019-04-11T06:52:12+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8aa278df0a338dfc05c731589051ab80373925c5'/>
<id>8aa278df0a338dfc05c731589051ab80373925c5</id>
<content type='text'>
For 32bit system, the OpenSBI (or BBL) will jump to 0x80400000 address
in S-mode whereas for 64bit system it will jump to 0x80200000 address
in S-mode.

Currently, the S-mode U-Boot sets SYS_TEXT_BASE to 0x80200000 for both
32bit and 64bit system. This breaks S-mode U-Boot for 32bit system.

This patch sets different SYS_TEXT_BASE for 32bit and 64bit system so
that S-mode U-Boot works fine for both.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Tested-by: Karsten Merker &lt;merker@debian.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For 32bit system, the OpenSBI (or BBL) will jump to 0x80400000 address
in S-mode whereas for 64bit system it will jump to 0x80200000 address
in S-mode.

Currently, the S-mode U-Boot sets SYS_TEXT_BASE to 0x80200000 for both
32bit and 64bit system. This breaks S-mode U-Boot for 32bit system.

This patch sets different SYS_TEXT_BASE for 32bit and 64bit system so
that S-mode U-Boot works fine for both.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Tested-by: Karsten Merker &lt;merker@debian.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: qemu: enable SMP</title>
<updated>2019-04-08T01:44:26+00:00</updated>
<author>
<name>Lukas Auer</name>
<email>lukas.auer@aisec.fraunhofer.de</email>
</author>
<published>2019-03-17T18:28:42+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d0a8fd3e4d2a5ab19b8f2d27d40dacb4942ba5a4'/>
<id>d0a8fd3e4d2a5ab19b8f2d27d40dacb4942ba5a4</id>
<content type='text'>
Signed-off-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: Rename cpu/qemu to cpu/generic</title>
<updated>2019-02-27T01:12:33+00:00</updated>
<author>
<name>Anup Patel</name>
<email>Anup.Patel@wdc.com</email>
</author>
<published>2019-02-25T08:14:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fdff1f96a6505bccb258f5b52e6c94c7e0b29512'/>
<id>fdff1f96a6505bccb258f5b52e6c94c7e0b29512</id>
<content type='text'>
The QEMU CPU support under arch/riscv is pretty much generic
and works fine for SiFive Unleashed as well. In fact, there
will be quite a few RISC-V SOCs for which QEMU CPU support
will work fine.

This patch renames cpu/qemu to cpu/generic to indicate the
above fact. If there are SOC specific errata workarounds
required in cpu/generic then those can be done at runtime
in cpu/generic based on CPU vendor specific DT compatible
string.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Alexander Graf &lt;agraf@suse.de&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The QEMU CPU support under arch/riscv is pretty much generic
and works fine for SiFive Unleashed as well. In fact, there
will be quite a few RISC-V SOCs for which QEMU CPU support
will work fine.

This patch renames cpu/qemu to cpu/generic to indicate the
above fact. If there are SOC specific errata workarounds
required in cpu/generic then those can be done at runtime
in cpu/generic based on CPU vendor specific DT compatible
string.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Alexander Graf &lt;agraf@suse.de&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
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