<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/board/emulation, branch v2021.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board/emulation?h=v2021.01</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/board/emulation?h=v2021.01'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2020-11-17T07:09:16Z</updated>
<entry>
<title>riscv: enable SATA disk on QEMU RISC-V</title>
<updated>2020-11-17T07:09:16Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2020-11-04T11:49:01Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2873ca2a7855d4a6f2c6cf931cb5a1e8dfce43c0'/>
<id>urn:sha1:2873ca2a7855d4a6f2c6cf931cb5a1e8dfce43c0</id>
<content type='text'>
Allow attaching a virtual SATA disk to QEMU RISC-V by implying
AHCI, AHCI_PCI, CMD_SCSI, DM_SCSI, PCI_INIT_R, SCSI, SCSI_AHCI.

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Reviewed-by: Bin Meng &lt;bin.meng@windriver.com&gt;
</content>
</entry>
<entry>
<title>riscv: sort SPECIFIC_OPTIONS</title>
<updated>2020-11-17T07:09:16Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2020-11-04T11:49:00Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=19dd274b5680940974977c0372e85b91bcbc006e'/>
<id>urn:sha1:19dd274b5680940974977c0372e85b91bcbc006e</id>
<content type='text'>
Sort implied options in BOARD_SPECIFIC_OPTIONS in the same sequence as in
.config.

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Reviewed-by: Bin Meng &lt;bin.meng@windriver.com&gt;
</content>
</entry>
<entry>
<title>x86: qemu: Remove dead code</title>
<updated>2020-09-01T09:00:27Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2020-09-01T08:33:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=365a581c1cbbb43c1d8da49d5bfd134530c1a621'/>
<id>urn:sha1:365a581c1cbbb43c1d8da49d5bfd134530c1a621</id>
<content type='text'>
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply replace the rule in it. We use stub C-file
like it's done for other boards.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>arm: qemu: override flash accessors to use virtualizable instructions</title>
<updated>2020-07-29T12:43:40Z</updated>
<author>
<name>Ard Biesheuvel</name>
<email>ardb@kernel.org</email>
</author>
<published>2020-07-07T10:07:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2e2c2a5e72a86238a0b4cd7885d3cbb403c8b882'/>
<id>urn:sha1:2e2c2a5e72a86238a0b4cd7885d3cbb403c8b882</id>
<content type='text'>
Some instructions in the ARM ISA have multiple output registers, such
as ldrd/ldp (load pair), where two registers are loaded from memory,
but also ldr with indexing, where the memory base register is incremented
as well when the value is loaded to the destination register.

MMIO emulation under KVM is based on using the architecturally defined
syndrome information that is provided when an exception is taken to the
hypervisor. This syndrome information describes whether the instruction
that triggered the exception is a load or a store, what the faulting
address was, and which register was the destination register.

This syndrome information can only describe one destination register, and
when the trapping instruction is one with multiple outputs, KVM throws an
error like

  kvm [615929]: Data abort outside memslots with no valid syndrome info

on the host and kills the QEMU process with the following error:

  U-Boot 2020.07-rc3-00208-g88bd5b179360-dirty (Jun 06 2020 - 11:59:22 +0200)

  DRAM:  1 GiB
  Flash: error: kvm run failed Function not implemented
  R00=00000001 R01=00000040 R02=7ee0ce20 R03=00000000
  R04=7ffd9eec R05=00000004 R06=7ffda3f8 R07=00000055
  R08=7ffd9eec R09=7ef0ded0 R10=7ee0ce20 R11=00000000
  R12=00000004 R13=7ee0cdf8 R14=00000000 R15=7ff72d08
  PSR=200001d3 --C- A svc32
  QEMU: Terminated

This means that, in order to run U-Boot in QEMU under KVM, we need to
avoid such instructions when accessing emulated devices. For the flash
in particular, which is a hybrid between a ROM (backed by a read-only
KVM memslot) when in array mode, and an emulated MMIO device (when in
write mode), we need to take care to only use instructions that KVM can
deal with when they trap.

So override the flash read accessors that are used when running on QEMU
under KVM. Note that the the 64-bit wide read and write accessors have
been omitted: they are never used when running under QEMU given that it
does not emulate CFI flash that supports it.

Signed-off-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>arm: qemu: implement enable_caches()</title>
<updated>2020-07-29T12:43:40Z</updated>
<author>
<name>Ard Biesheuvel</name>
<email>ardb@kernel.org</email>
</author>
<published>2020-07-07T10:07:09Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3fa914af821496bde52d8be510224f5e69c9c8b9'/>
<id>urn:sha1:3fa914af821496bde52d8be510224f5e69c9c8b9</id>
<content type='text'>
Add an override for enable_caches to enable the I and D caches, along
with the cached 1:1 mapping of all of DRAM. This is needed for running
U-Boot under virtualization with QEMU/kvm.

Signed-off-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
Reviewed-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>riscv: qemu: Add syscon reboot and poweroff support</title>
<updated>2020-07-24T06:55:55Z</updated>
<author>
<name>Bin Meng</name>
<email>bin.meng@windriver.com</email>
</author>
<published>2020-06-23T05:29:45Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a0cc38ab44b0fa8af65632cbea1b13630195f03d'/>
<id>urn:sha1:a0cc38ab44b0fa8af65632cbea1b13630195f03d</id>
<content type='text'>
This adds syscon reboot and poweroff support to QEMU RISC-V.

Signed-off-by: Bin Meng &lt;bin.meng@windriver.com&gt;
Reviewed-by: Pragnesh Patel &lt;pragnesh.patel@sifive.com&gt;
</content>
</entry>
<entry>
<title>common: Drop log.h from common header</title>
<updated>2020-05-19T01:19:18Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:05Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f7ae49fc4f363a803dab3be078e93ead8e75a8e9'/>
<id>urn:sha1:f7ae49fc4f363a803dab3be078e93ead8e75a8e9</id>
<content type='text'>
Move this header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>common: Drop init.h from common header</title>
<updated>2020-05-18T21:33:33Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:02Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=691d719db7183dfb1d1360efed4c5e9f6899095f'/>
<id>urn:sha1:691d719db7183dfb1d1360efed4c5e9f6899095f</id>
<content type='text'>
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>common: Drop image.h from common header</title>
<updated>2020-05-18T21:33:33Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:01Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4d72caa5b96b71e49b63f98bd8548b194380b544'/>
<id>urn:sha1:4d72caa5b96b71e49b63f98bd8548b194380b544</id>
<content type='text'>
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Revert "riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL"</title>
<updated>2020-04-23T02:13:35Z</updated>
<author>
<name>Lukas Auer</name>
<email>lukas.auer@aisec.fraunhofer.de</email>
</author>
<published>2020-04-14T21:24:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=846b6120140ae98ca88d245fb10955d3c6980603'/>
<id>urn:sha1:846b6120140ae98ca88d245fb10955d3c6980603</id>
<content type='text'>
The commit was added as a workaround required in QEMU when using BBL as
the supervisor binary interface (SBI) for Linux. We are now using
OpenSBI to provide the SBI, the workaround is therefore not required
anymore and can be removed.

This reverts commit 897206c5cc5c6ac0dc2ab851044e42baada3785b.

Signed-off-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
</feed>
