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<title>u-boot.git/board/freescale/common, branch v2016.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board/freescale/common?h=v2016.01</id>
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<updated>2016-01-07T16:48:25Z</updated>
<entry>
<title>pfuze: Fix unsigned variable for less-than-zero comparison</title>
<updated>2016-01-07T16:48:25Z</updated>
<author>
<name>Ye.Li</name>
<email>B37916@freescale.com</email>
</author>
<published>2016-01-04T07:26:30Z</published>
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<id>urn:sha1:7ea191aa10c43b5497d171ab6f48e633e6779468</id>
<content type='text'>
According to the Coverity result, a unsigned int variable is used fo less-
than-zero comparison, the result is never true. Need to fix the variable
type to signed int.

Signed-off-by: Ye.Li &lt;B37916@freescale.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Przemyslaw Marczak &lt;p.marczak@samsung.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Reviewed-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>armv8/ls1043ardb: add SECURE BOOT target for NOR</title>
<updated>2015-12-15T00:57:35Z</updated>
<author>
<name>Aneesh Bansal</name>
<email>aneesh.bansal@freescale.com</email>
</author>
<published>2015-12-08T08:24:29Z</published>
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<id>urn:sha1:9711f52806655bcfa28fe5594b91fed430beb72e</id>
<content type='text'>
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.

Signed-off-by: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>freescale: fman: make sure phy-handle property is big endian</title>
<updated>2015-12-14T02:27:28Z</updated>
<author>
<name>Shaohui Xie</name>
<email>Shaohui.Xie@freescale.com</email>
</author>
<published>2015-11-10T11:20:16Z</published>
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<id>urn:sha1:1aaf3f9ae471929a70509f86a48a61da6fbfb19f</id>
<content type='text'>
When creating phy-handle property, an unsigned int value is created by
fdt_create_phandle, and memcpy is used to get the value, since DTS is
big endian, the value cannot be used directly on little endian SoCs,
it should be converted by cpu_to_fdt32.

Signed-off-by: Shaohui Xie &lt;Shaohui.Xie@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>armv8/ls1043aqds: add LS1043AQDS board support</title>
<updated>2015-11-30T17:11:10Z</updated>
<author>
<name>Shaohui Xie</name>
<email>Shaohui.Xie@freescale.com</email>
</author>
<published>2015-11-11T09:58:37Z</published>
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<id>urn:sha1:02b5d2ed867e92b56fa54b94685edb196fde98bf</id>
<content type='text'>
LS1043AQDS Specification:
-------------------------
Memory subsystem:
 * 2GByte DDR4 DIMM
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 16 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * Two RGMII ports
 * XFI 10G port
 * SGMII
 * QSGMII with 4x 1G ports

PCIe: supports Gen 1 and Gen 2

SATA 3.0: one SATA 3.0 port

USB 3.0: two micro AB connector and one type A connector

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Shaohui Xie &lt;Shaohui.Xie@freescale.com&gt;
Signed-off-by: Mingkai Hu &lt;Mingkai.Hu@freescale.com&gt;
Signed-off-by: Hou Zhiqiang &lt;B48286@freescale.com&gt;
Signed-off-by: Gong Qianyu &lt;Qianyu.Gong@freescale.com&gt;
[York Sun: Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>mmc: fsl_esdhc: enable EVDD automatic control for SD/MMC Legacy Adapter Card</title>
<updated>2015-11-02T16:50:29Z</updated>
<author>
<name>Yangbo Lu</name>
<email>yangbo.lu@freescale.com</email>
</author>
<published>2015-09-17T02:27:48Z</published>
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<id>urn:sha1:bf50be835ed1c0e2875ff7672381944eeab8695d</id>
<content type='text'>
When detecting SDHC Adapter Card Type 2(SD/MMC Legacy Adapter Card),
enable EVDD automatic control via SDHC_VS. This could support SD card
IO voltage switching for UHS-1 speed mode.

Signed-off-by: Yangbo Lu &lt;yangbo.lu@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>mmc: fsl_esdhc: enable dat[4:7] for eMMC4.5 Adapter Card</title>
<updated>2015-11-02T16:49:51Z</updated>
<author>
<name>Yangbo Lu</name>
<email>yangbo.lu@freescale.com</email>
</author>
<published>2015-09-17T02:27:12Z</published>
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<id>urn:sha1:cdc69550d21f38c99a3c2428598f1a6f126e955e</id>
<content type='text'>
If adapter card type identification is supported for platform, we would
enable dat[4:7] for eMMC4.5 Adapter Card.

Signed-off-by: Yangbo Lu &lt;yangbo.lu@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>arm: ls1021atwr: optimize the deep sleep latency</title>
<updated>2015-10-30T16:19:48Z</updated>
<author>
<name>tang yuantian</name>
<email>Yuantian.Tang@freescale.com</email>
</author>
<published>2015-09-24T07:52:02Z</published>
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<id>urn:sha1:0210a3698862801169e3149475174b5268602a93</id>
<content type='text'>
It will take more than 1s when wake up from deep sleep. Most of the
time is spent on outputing information. This patch reduced the deep
sleep latency by:
1. avoid outputing system informaton
2. remove flush cache after DDR restore
3. skip reloading second stage uboot binary when SD boot

Signed-off-by: Tang Yuantian &lt;Yuantian.Tang@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>SECURE_BOOT: Correct reading of ITS bit</title>
<updated>2015-10-30T16:19:47Z</updated>
<author>
<name>Aneesh Bansal</name>
<email>aneesh.bansal@freescale.com</email>
</author>
<published>2015-10-12T16:35:50Z</published>
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<id>urn:sha1:6ec9aef2cef311c57652e8d17b09eceac2cebb06</id>
<content type='text'>
The ITS bit was being read incorrectly beacause of operator
precedence. The same ahs been corrected.

Signed-off-by: Lawish Deshmukh &lt;lawish.deshmukh@freescale.com&gt;
Signed-off-by: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>armv8/ls1043a: Add Fman support</title>
<updated>2015-10-29T17:34:01Z</updated>
<author>
<name>Shaohui Xie</name>
<email>Shaohui.Xie@freescale.com</email>
</author>
<published>2015-10-26T11:47:54Z</published>
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<id>urn:sha1:e82973414da105c1b14c822f12cb296f69ca2001</id>
<content type='text'>
Signed-off-by: Hou Zhiqiang &lt;B48286@freescale.com&gt;
Signed-off-by: Shaohui Xie &lt;Shaohui.Xie@freescale.com&gt;
Signed-off-by: Mingkai Hu &lt;Mingkai.Hu@freescale.com&gt;
Signed-off-by: Gong Qianyu &lt;Qianyu.Gong@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>armv7/ls1021a: move ns_access to common file</title>
<updated>2015-10-29T17:33:58Z</updated>
<author>
<name>Mingkai Hu</name>
<email>Mingkai.Hu@freescale.com</email>
</author>
<published>2015-10-26T11:47:41Z</published>
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<id>urn:sha1:435acd83b2b4f31699732f090d28d66cabb05912</id>
<content type='text'>
Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.

Signed-off-by: Mingkai Hu &lt;Mingkai.Hu@freescale.com&gt;
Signed-off-by: Hou Zhiqiang &lt;B48286@freescale.com&gt;
Signed-off-by: Gong Qianyu &lt;Qianyu.Gong@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
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