u-boot.git/board/freescale, branch v2009.01

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

2009-01-13T23:26:48Z

Some changes of TLB entry setting for MPC8572DS

2009-01-13T22:58:46Z

- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 can not access PIXIS_BASE anymore (any access will cause DataTLBError exception) - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board. Signed-off-by: Haiying Wang

Change PCIE1&2 deciide logic on MPC8544DS board more readable

2009-01-13T22:32:53Z

The IO port selection for MPC8544DS board: Port cfg_io_ports PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 PCIE2 0x4, 0x5, 0x6, 0x7 PCIE3 0x6, 0x7 This patch changes the PCIE12 and PCIE2 logic more readable. Signed-off-by: Roy Zang

PCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bit

2009-01-13T22:32:52Z

PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of PCIE1 bit. On MPC8572DS board, PCIE refers to PCIE1. Signed-off-by: Roy Zang

Fix IO port selection issue on MPC8544DS and MPC8572DS boards

2009-01-13T22:32:52Z

The IO port selection is not correct on MPC8572DS and MPC8544DS board. This patch fixes this issue. For MPC8572 Port cfg_io_ports PCIE1 0x2, 0x3, 0x7, 0xb, 0xc, 0xf PCIE2 0x3, 0x7 PCIE3 0x7 For MPC8544 Port cfg_io_ports PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 PCIE2 0x4, 0x5, 0x6, 0x7 PCIE3 0x6, 0x7 Signed-off-by: Roy Zang

mpc8610hpcd: Fix PCI mapping concepts

2009-01-13T21:27:46Z

Rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. This makes the code easier to read and understand, and facilitates mapping changes going forward. Signed-off-by: Becky Bruce

mpc8xxx: LCRR[CLKDIV] is sometimes five bits

2008-12-20T00:20:25Z

On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho Acked-by: Kumar Gala Acked-by: Jon Loeliger

85xx: Add PORDEVSR_PCI1 define

2008-12-04T09:15:43Z

Add define used to determine if PCI1 interface is in PCI or PCIX mode. Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1 Signed-off-by: Peter Tyser Signed-off-by: Andy Fleming

85xx: Add CPU 2 errata workaround to all 8548 boards

2008-12-04T04:46:42Z

All mpc8548-based boards should implement the suggested workaround to CPU 2 errata. Without the workaround, its possible for the 8548's core to hang while executing a msync or mbar 0 instruction and a snoopable transaction from an I/O master tagged to make quick forward progress is present. Signed-off-by: Peter Tyser Acked-by: Andy Fleming

85xx: the DDR tlb is missed for the !CONFIG_SPD_EEPROM case

2008-12-04T04:46:05Z

we need TLB entry for DDR at !SPD case. Signed-off-by: Dave Liu Acked-by: Andy Fleming