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<title>u-boot.git/board/freescale, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board/freescale?h=v2016.09</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/board/freescale?h=v2016.09'/>
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<updated>2016-09-06T16:22:48Z</updated>
<entry>
<title>mx6ul_14x14_ev: Enable the CCGR clocks earlier</title>
<updated>2016-09-06T16:22:48Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2016-08-29T23:37:18Z</published>
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<id>urn:sha1:ab25f0f69f2024d14bfa739261a3f56d363ead30</id>
<content type='text'>
To be in the safe side we need to enable the CCGR clocks prior
to calling arch_cpu_init().

Inspired by Tim Harvey's commit d783c2744f9 ("imx: ventana: fix boot to SD").

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Reviewed-by: Eric Nelson &lt;eric@nelint.com&gt;
Tested-by: Eric Nelson &lt;eric@nelint.com&gt;
</content>
</entry>
<entry>
<title>mx6ul_14x14_evk: Adjust SPL DDR3 settings</title>
<updated>2016-09-06T16:22:48Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2016-08-29T23:37:17Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b343417e2959d043ffd831fd15b08e2a49de6340'/>
<id>urn:sha1:b343417e2959d043ffd831fd15b08e2a49de6340</id>
<content type='text'>
Adjust DDR3 initialization done in SPL by comparing them against
the NXP DCD table.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Reviewed-by: Eric Nelson &lt;eric@nelint.com&gt;
</content>
</entry>
<entry>
<title>mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang</title>
<updated>2016-09-06T16:22:48Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2016-08-29T23:37:16Z</published>
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<id>urn:sha1:7dbda25ecd6d7cba13d29161675309ca43e3ba12</id>
<content type='text'>
When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk,
we observe a hang when going into the lowest operational point of cpufreq.

This hang issue does not happen on the NXP U-Boot version.

After comparing the SPL DDR initialization against the DCD table
from NXP U-Boot, the key difference that causes the hang is the
MDREF register setting:

DATA 4 0x021B0020 0x00000800

,which means:

REF_SEL = 0 --&gt; Periodic refresh cycle: 64kHz
REFR = 1 ---&gt; Refresh Rate - 2 refreshes

So adjust the MDREF initialization for mx6ul_evk accordingly
to fix the kernel hang issue at low bus frequency.

Reported-by: Eric Nelson &lt;eric@nelint.com&gt;
Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Reviewed-by: Eric Nelson &lt;eric@nelint.com&gt;
</content>
</entry>
<entry>
<title>mx6: ddr: Allow changing REFSEL and REFR fields</title>
<updated>2016-09-06T16:22:48Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2016-08-29T23:37:15Z</published>
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<id>urn:sha1:edf0093732225c2fd0791c3864e9a3eef1f92f19</id>
<content type='text'>
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.

Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:

$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4      0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800

So introduce a mechanism for users to be able to configure
REFSEL and REFR fields as needed.

Keep all the mx6 SPL users in their current REF_SEL and REFR values,
so no functional changes for the existing users.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Reviewed-by: Eric Nelson &lt;eric@nelint.com&gt;
</content>
</entry>
<entry>
<title>mx7dsabresd: Directly write to register LDOGCTL</title>
<updated>2016-09-06T16:22:48Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2016-08-17T12:46:24Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=946db0cbd01090b35eb1439fa7c4ca7e015fc18b'/>
<id>urn:sha1:946db0cbd01090b35eb1439fa7c4ca7e015fc18b</id>
<content type='text'>
Register LDOGCTL contains only bit 0 as a valid bit, so there is no need
to do a read-modify-write operation.

Simplify the code by writing directly to this register.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
</content>
</entry>
<entry>
<title>mx7dsabresd: Directly write to register LDOGCTL</title>
<updated>2016-09-06T16:22:48Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2016-08-17T12:46:23Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=78eed0a6d56fd5e4cdf71ffc7ab4e74aed62a5c9'/>
<id>urn:sha1:78eed0a6d56fd5e4cdf71ffc7ab4e74aed62a5c9</id>
<content type='text'>
Register LDOGCTL contains only bit 0 as a valid bit, so there is no need
to do a read-modify-write operation.

Simplify the code by writing directly to this register.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
</content>
</entry>
<entry>
<title>mx6ul_14x14_evk: don't use array for SD2 card detect pad</title>
<updated>2016-09-06T16:22:48Z</updated>
<author>
<name>Eric Nelson</name>
<email>eric@nelint.com</email>
</author>
<published>2016-08-05T23:51:17Z</published>
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<id>urn:sha1:eb3813ad1afb29401fce20e9553df71e98f4aeec</id>
<content type='text'>
Only a single pad is changed to change sdhc2_dat3 from an
SDIO pin to and from GPIO4:5, so remove the array and use
the imx_iomux_v3_setup_pad() routine.

Signed-off-by: Eric Nelson &lt;eric@nelint.com&gt;
Reviewed-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
</content>
</entry>
<entry>
<title>mx7dsabresd: Print secure/non-secure mode info</title>
<updated>2016-09-06T16:22:48Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2016-07-28T23:49:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=76b21efd555b9bc7e4e7fb8ebc7de2558403731a'/>
<id>urn:sha1:76b21efd555b9bc7e4e7fb8ebc7de2558403731a</id>
<content type='text'>
mx7dsabresd has two targets:

- mx7dsabresd_defconfig: boots in non-secure mode
- mx7dsabresd_secure_defconfig: boots in secure mode

Print the mode that is being used to help users to easily identify
which target is running on the board.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
</content>
</entry>
<entry>
<title>treewide: fix "followings" to "following"</title>
<updated>2016-08-26T21:04:58Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2016-08-21T07:12:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c21fc7e223ebad72735b9d02bcbd8878ae026fef'/>
<id>urn:sha1:c21fc7e223ebad72735b9d02bcbd8878ae026fef</id>
<content type='text'>
Most of them are my mistakes.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>board/freescale: Update MAINTAINERS files</title>
<updated>2016-08-02T16:47:34Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-07-29T15:46:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=473af36a889d3a7e6faad1ec95b926a21c834bf8'/>
<id>urn:sha1:473af36a889d3a7e6faad1ec95b926a21c834bf8</id>
<content type='text'>
Update maintainers for secure boot targets.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
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