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<title>u-boot.git/board/gateworks/venice, branch master</title>
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<id>http://cgit.235523.xyz/u-boot.git/atom/board/gateworks/venice?h=master</id>
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<updated>2026-04-27T17:26:40Z</updated>
<entry>
<title>rename NET to NET_LEGACY</title>
<updated>2026-04-27T17:26:40Z</updated>
<author>
<name>Quentin Schulz</name>
<email>quentin.schulz@cherry.de</email>
</author>
<published>2026-04-20T11:36:08Z</published>
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<id>urn:sha1:b8cd4442257af4ec754838ea179568e0e7360b8f</id>
<content type='text'>
Highlight that NET really is the legacy networking stack by renaming the
option to NET_LEGACY.

This requires us to add an SPL_NET_LEGACY alias to SPL_NET as otherwise
CONFIG_IS_ENABLED(NET_LEGACY) will not work for SPL.

The "depends on !NET_LWIP" for SPL_NET clearly highlights that it is
using the legacy networking app so this seems fine to do.

This also has the benefit of removing potential confusion on NET being a
specific networking stack instead of "any" network stack.

Signed-off-by: Quentin Schulz &lt;quentin.schulz@cherry.de&gt;
Acked-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;
Reviewed-by: Peter Robinson &lt;pbrobinson@gmail.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>venice: display DRAM MR registers and decoding if debug enabled</title>
<updated>2025-07-17T12:58:42Z</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2025-07-14T17:23:04Z</published>
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<id>urn:sha1:6dc91a840810b7a35c78ac14e9868db462ae2039</id>
<content type='text'>
While this is interesting and useful for debugging there isn't extremely
useful information so we will only show it if debug is enabled.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
</content>
</entry>
<entry>
<title>venice: lpddr4_timing_imx8mm: update ddr phy config for mscale_v3.10</title>
<updated>2025-07-17T12:58:42Z</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2025-07-14T17:23:03Z</published>
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<id>urn:sha1:2c692bff83172b114329b2204b2fc8996e01ee7e</id>
<content type='text'>
Update the ddr phy config values to those created by the mscale_v3.10
tool. The original values were obtained using mscale_v3.10. The v3.10
tool removed ddr phy register values of 0x0.

This has no functional change but makes comparing and patching ddr
configuration easier in addition to slightly shrinking the DRAM config
size.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
</content>
</entry>
<entry>
<title>venice: lpddr4_timing_imx8mm: add 4gb single die support</title>
<updated>2025-07-17T12:58:42Z</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2025-07-14T17:23:02Z</published>
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<id>urn:sha1:c2bfdb24c8068e950c5229648271b97a31b2143e</id>
<content type='text'>
Add dram support for the MT53E1G32D2FW-046 RevC part which is a single die
32Gbit density part vs RevA/B which were dual-die parts:
 - use a previously unused EEPROM byte to denote a variant of the
   base config to be patched
 - add a dram description string
 - return the board struct from eeprom_init and pass it to the
   spl_dram_init function so that it has access to the EEPROM
 - move ddr_init into the spl_dram_init so that it can be patched
   in the per-soc init function

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
</content>
</entry>
<entry>
<title>venice: lpddr4_timing_imx8mm: add DDRC_ADDRMAP7 config</title>
<updated>2025-07-17T12:58:42Z</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2025-07-14T17:23:01Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=393c3de7715be85790fcaf08772f219013837658'/>
<id>urn:sha1:393c3de7715be85790fcaf08772f219013837658</id>
<content type='text'>
Add the configuration register for DDRC_ADDRMAP7 which was added in the
RAP spreadsheet v19. This has no functional change but allows DRAM
configuration to be patched in a later commit.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
</content>
</entry>
<entry>
<title>board: venice: append configuration string to model</title>
<updated>2025-05-30T22:10:56Z</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2025-05-23T17:20:17Z</published>
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<id>urn:sha1:314469b6bad1892b04c4cbc10e91f9cec30bdec5</id>
<content type='text'>
Append the optional board configuration string to the model info.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>board: venice: update model representation for venice-flex</title>
<updated>2025-05-30T22:10:56Z</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2025-05-23T17:20:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=41bc2d5334fbd23fcba6853d90c6f45b1400dd87'/>
<id>urn:sha1:41bc2d5334fbd23fcba6853d90c6f45b1400dd87</id>
<content type='text'>
Update the model string representation for the Venice-Flex product
family (GW8xxx).

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>board: venice: add FSA support</title>
<updated>2025-05-30T22:10:56Z</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2025-05-23T17:20:15Z</published>
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<id>urn:sha1:da9e2218afc2fd8ac9e4cd4e4dd02a9a2e83e6db</id>
<content type='text'>
The Gateworks Flexible Socket Adapters adapt common
busses such as SDIO/UART/USB/PCI to various connectors
such as M.2 B-Key, M.2 E-Key, M.2 M-Key, and MiniPCIe.

Each FSA has an EEPROM onboard describing its details as well as an
optional port-expander for configurable GPIO's.

Add support for identifying the FSA's and configuring their
details such as user description and GPIO's:
 - enable pca953x, pca954x and eeprom support for communicating
   with the I2C eeprom and gpio port expander on the FSA
 - add FSA detection support
 - add FSA gpio configuration support

Each FSA is identified in the device-tree by an alias to it's I2C
bus where an eeprom@54 node must exist as well as an gpio@20 node
for an io-expander. These nodes must be enabled so that
they can be probed to determine if they are actually present in
the system. If not present or not enabled the gpio expander can
not be used. This also requires livetree as the gpio expander
node if not present must be disabled.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>board: venice: flip logic for GSC supervisor enable</title>
<updated>2025-05-30T22:10:56Z</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2025-05-23T17:20:13Z</published>
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<id>urn:sha1:5e726768905bd00082b711e05e3021ebe36c1767</id>
<content type='text'>
Flip the logic used to determine if a board has the proper hardware to
support enabling the GSC voltage supervisor so that we do not need to
keep adding new models to the list.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>board: venice: use SOM model for PMIC adjustment on SOM</title>
<updated>2025-05-30T22:10:56Z</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2025-05-23T17:20:12Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b1ead5a2240002f880e6560bc7715eb6b250dd6d'/>
<id>urn:sha1:b1ead5a2240002f880e6560bc7715eb6b250dd6d</id>
<content type='text'>
Use the SOM model to adjust PMIC settings on SOM's.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
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