Currently MX6 SPL DDR initialization hardcodes the REF_SEL and REFR fields of the MDREF register as 1 and 7, respectively for DDR3 and 0 and 3 for LPDDR2. Looking at the MDREF initialization done via DCD we see that boards do need to initialize these fields differently: $ git grep 0x021b0020 board/ board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */ board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800 board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800 board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800 So introduce a mechanism for users to be able to configure REFSEL and REFR fields as needed. Keep all the mx6 SPL users in their current REF_SEL and REFR values, so no functional changes for the existing users. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
Added removal of the fsl,ext-reset-output property in the wdog node for board revisions that pre-date the addition of the external watchdog reset signal. This property is a recent addition to mainline linux kernel in order to specify that the IMX watchdog external reset should be used instead of the internal chip-level reset. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Re-factor the board-specific dt fixups so that they are easier to follow and extend in the future: - use defines for DT paths - use switch/case per board - order models numerically There is no functional change in the code Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The hwconfig env var allows user to control hardware specific configuration of board specific features but not all Ventana boards have the same features. We will use the magic default value of "_UNKNOWN_" to signify that the bootloader should create this based on detected board model. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The GW5520 has 10 DIO's instead of the typical 4 found on the Ventana product family. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Replace the static list of board-specific digital I/O's with a dynamic list. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Not all Ventana boards have an RS232 transceiver, make it board specific. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Ventana boards with a PCI Marvell Sky2 GigE MAC require the MAC address to be placed in a DT node in order for the mainline linux driver to obtain it. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The GW16082 mini-PCI expansion mezzanine uses a TI XIO2001 PCIe-to-PCI bridge with legacy INTA/B/C/D interrupts. These interrupts are assigned in the reverse order according to the PCI spec. If the TI bridge is found on the Ventana PCI bus, add device-tree nodes according to bus enumeration explicitly defining the interrupt mapping to override the default PCI mapping in the Linux kernel. This allows the GW16082 to work with upstream kernels that support device-tree irq parsing. Signed-off-by: Tim Harvey <tharvey@gateworks.com>