u-boot.git/board/ge, branch v2017.07

board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue

2017-03-26T14:58:11Z

Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register to avoid the voltage peak issue while we do the IEEE PHY comformance test Signed-off-by: Ken Lin Reviewed-by: Stefano Babic Acked-by: Ian Ray

board: ge: bx50v3: fix AR8033 reset timing issue

2017-03-26T14:58:08Z

Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet Signed-off-by: Ken Lin Reviewed-by: Stefano Babic Acked-by: Ian Ray

board: ge: bx50v3: add the PMIC configuration support

2016-11-29T15:42:53Z

Change the PMIC bulk configuration from auto mode to sync mode to avoid voltage dropout issue seen in auto mode. Signed-off-by: Ken Lin Signed-off-by: Akshay Bhat

treewide: replace #include with

2016-09-23T21:55:42Z

Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap ) Replace all include directives for with . Signed-off-by: Masahiro Yamada [trini: Fixup include/clk.] Signed-off-by: Tom Rini

bx50v3: Use imx_ddr_size() for calculating the DDR size

2016-07-28T11:27:20Z

imx_ddr_size() can be used to calculate the DDR size in runtime. By using this function we no longer need to define PHYS_SDRAM_SIZE. Cc: Martin Donnelly Signed-off-by: Fabio Estevam

board: ge: bx50v3: don't configure the backlight when there's no display

2016-06-07T16:13:05Z

Don't try to configure the backlight when CONFIG_VIDEO_IPUV3 isn't set. Signed-off-by: Andrew Shadura

board: ge: bx50v3: Fix to meet LVDS display power on timing

2016-04-19T14:05:51Z

On a reset/reboot, the display power needs to be off for atleast 500ms before turning it back on. So add a delay to the boot process to meet the display timing requirement. Signed-off-by: Akshay Bhat Cc: Stefano Babic

board: ge: bx50v3: Use pwm for display backlight

2016-04-19T14:05:51Z

Setup the LCD backlight brightness control pin to use PWM Signed-off-by: Akshay Bhat Cc: Stefano Babic

board: ge: bx50v3: Setup LDB_DI_CLK source

2016-04-19T14:05:13Z

To generate accurate pixel clocks required by the displays we need to set the ldb_di_clk source on bx50v3 to PLL3 and b850v3 to PLL5. Since PLL5 is disabled on reset, we need to enable PLL5. Signed-off-by: Akshay Bhat Cc: Stefano Babic

board: ge: bx50v3: Split display setup function

2016-04-19T14:05:13Z

B450v3/B650v3 uses single channel LVDS and does not support HDMI. B850v3 uses dual channel LVDS and supports HDMI. Hence split the display setup into two different functions. Signed-off-by: Akshay Bhat Cc: Stefano Babic