u-boot.git/board/google, branch v2015.01 Unnamed repository; edit this file 'description' to name the repository. x86: ich6-gpio: Add Intel Tunnel Creek GPIO support 2014-12-19T00:26:06+00:00 Bin Meng bmeng.cn@gmail.com 2014-12-17T07:50:38+00:00 b71eec3129c2626bfb1e98141b317d958e3cf384 Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> 
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.

Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
x86: ich6-gpio: Move setup_pch_gpios() to board support codes 2014-12-14T05:32:04+00:00 Bin Meng bmeng.cn@gmail.com 2014-12-12T13:05:23+00:00 2795573a8c9c62db7b4bcf4bddf54d73b6ae61d3 Movie setup_pch_gpios() in the ich6-gpio driver to the board support codes, so that the driver does not need to know any platform specific stuff (ie: include the platform specifc chipset header file). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> 
Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
x86: Make ROM_SIZE configurable in Kconfig 2014-12-14T05:32:03+00:00 Bin Meng bmeng.cn@gmail.com 2014-12-12T13:05:19+00:00 64542f4616c484142b90534f9f174a632d7d1904 Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This will not be the case when adding additional board support. Hence we make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the board Kconfig file select the default ROM_SIZE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> 
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
x86: chromebook_link: Enable the Chrome OS EC 2014-11-25T14:11:17+00:00 Simon Glass sjg@chromium.org 2014-11-15T03:56:45+00:00 22e131ca00ed42cd7485aa1821dc3051bd762a3e Enable the Chrome OS EC so that it can be used from U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> 
Enable the Chrome OS EC so that it can be used from U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Remove board_early_init_r() 2014-11-25T13:33:59+00:00 Simon Glass sjg@chromium.org 2014-11-15T01:18:22+00:00 65990d568074ad878cbc7e4eb1053508e3707cb6 This function is not needed. Remove it to improve the generic init sequence slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
This function is not needed. Remove it to improve the generic init sequence
slightly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: chromebook_link: Enable GPIO support 2014-11-21T06:34:15+00:00 Simon Glass sjg@chromium.org 2014-11-13T05:42:25+00:00 437c2b7cd04f017cf79dcde63e7d9035f8cd99e5 Enable GPIO support and provide the required GPIO setup information to the driver. Signed-off-by: Simon Glass <sjg@chromium.org> 
Enable GPIO support and provide the required GPIO setup information to
the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
x86: chromebook_link: Implement CAR support (cache as RAM) 2014-11-21T06:34:11+00:00 Simon Glass sjg@chromium.org 2014-11-13T05:42:10+00:00 70a09c6c3dc25b200a9d0475afcf5dfc9836b18e Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org> 
Add support for CAR so that we have memory to use prior to DRAM init.
On link there is a total of 128KB of CAR available, although some is
used for the memory reference code.

Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Emit post codes in startup code for Chromebooks 2014-11-21T06:34:11+00:00 Simon Glass sjg@chromium.org 2014-11-13T05:42:09+00:00 d1cd045982b1e1e4db2c1cc2b2b932f739b78a11 On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died. On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
see where the code got to before it died.

On modern hardware these codes are not normally visible. On Chromebooks
they are displayed by the Embedded Controller (EC), so it is useful to emit
them. We must enable this feature for the EC to see the codes, so add an
option for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: Add chromebook_link board 2014-11-21T06:34:11+00:00 Simon Glass sjg@chromium.org 2014-11-13T05:42:07+00:00 8ef07571a0300e6ae84931c63d5eb3b2310c8aba This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> 
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.

This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.

Signed-off-by: Simon Glass <sjg@chromium.org>