u-boot.git/board/google, branch v2016.07 Unnamed repository; edit this file 'description' to name the repository. x86: Add support for the samus chromebook 2016-03-17T02:27:27+00:00 Simon Glass sjg@chromium.org 2016-03-16T13:44:43+00:00 374e78efb0c6739c8c700325acca769d7a9e47de This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.

Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard

Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).

The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: Drop all the old pin configuration code 2016-03-17T02:27:25+00:00 Simon Glass sjg@chromium.org 2016-03-12T05:07:15+00:00 779653b0cbe3f634632bc4ecae1ce5df84638326 We don't need this anymore - we can use device tree and the new pinconfig driver instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
We don't need this anymore - we can use device tree and the new pinconfig
driver instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: ivybridge: Move northbridge and PCH init into drivers 2016-01-24T04:08:17+00:00 Simon Glass sjg@chromium.org 2016-01-17T23:11:31+00:00 9ed781a6ffba48d75b3ae0a0058ca439b8e178c2 Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Instead of calling the northbridge and PCH init from bd82x6x_init_extra()
when the PCI bus is probed, call it from the respective drivers. Also drop
the Northbridge init as it has no effect. The registers it touches appear to
be read-only.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: ivybridge: Do not require HAVE_INTEL_ME 2016-01-13T04:20:15+00:00 Bin Meng bmeng.cn@gmail.com 2015-12-11T10:55:49+00:00 fa331fad1eee0bd86470b49a905ed176aa412b9a Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> 
Do not set HAVE_INTEL_ME by default as for some cases Intel ME
firmware even does not reside on the same SPI flash as U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
x86: Remove HAVE_ACPI_RESUME 2015-12-09T09:44:56+00:00 Bin Meng bmeng.cn@gmail.com 2015-11-26T01:46:09+00:00 789fa275b3750e60c60cb3d18eabc9467892c257 These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> 
These are currently dead codes. Until we have complete ACPI support,
we don't know if it works or not. Remove to avoid confusion.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
x86: Remove CPU_INTEL_SOCKET_RPGA989 2015-12-09T09:44:54+00:00 Bin Meng bmeng.cn@gmail.com 2015-11-26T01:46:08+00:00 d475d59020af32bd5b55ca48a5bc73213e53a7c8 This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> 
This Kconfig option name indicates it has something to do with cpu
socket, however it is actually not the case. Remove it and move
options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
x86: Clean up ivybridge/chrome Kconfig options 2015-12-09T09:44:52+00:00 Bin Meng bmeng.cn@gmail.com 2015-11-26T01:46:07+00:00 efe2d80cca4822ce6c435993e01467eeee8babfb There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> 
There are some options which are never used, and also some options
which are selected by others but have never been a Kconfg option.
Clean these up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
rockchip: Add basic support for jerry 2015-09-03T03:28:24+00:00 Simon Glass sjg@chromium.org 2015-08-30T22:55:42+00:00 e2e947ff6ba676e5ba84639fe6f2766aa683e181 This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org> 
This builds and displays an SPL message, but does not function beyond that.

Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Remove MARK_GRAPHICS_MEM_WRCOMB 2015-07-15T00:03:18+00:00 Bin Meng bmeng.cn@gmail.com 2015-07-06T08:31:34+00:00 9e3a7c9bac35d47b7a021e311147ba0b5a128b08 MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code, hence remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> 
MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code,
hence remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
arch: Make board selection choices optional 2015-05-12T22:10:02+00:00 Joe Hershberger joe.hershberger@ni.com 2015-05-12T19:46:23+00:00 a26cd04920dc069fd6e91abb785426cf6c29f45f By making the board selections optional, every defconfig will include the board selection when running savedefconfig so if a new board is added to the top of the list of choices the former top's defconfig will still be correct. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Rini <trini@konsulko.com> 
By making the board selections optional, every defconfig will include
the board selection when running savedefconfig so if a new board is
added to the top of the list of choices the former top's defconfig will
still be correct.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Rini <trini@konsulko.com>