u-boot.git/board/google, branch v2017.01 Unnamed repository; edit this file 'description' to name the repository. rockchip: Add support for veyron-minnie (ASUS Chromebook Flip) 2016-11-26T00:59:32+00:00 Simon Glass sjg@chromium.org 2016-11-13T21:24:54+00:00 c420ef67e5799d80b807c2866576bf3881893cbf This adds support for the Asus Chromebook Flip, an RK3288-based clamshell device which can flip into 'tablet' mode. The device tree file comes from Linux v4.8. The SDRAM parameters are for 4GB Samsung LPDDR3. Signed-off-by: Simon Glass <sjg@chromium.org> 
This adds support for the Asus Chromebook Flip, an RK3288-based clamshell
device which can flip into 'tablet' mode. The device tree file comes from
Linux v4.8. The SDRAM parameters are for 4GB Samsung LPDDR3.

Signed-off-by: Simon Glass <sjg@chromium.org>
rockchip: Add support for veyron-mickey (Chromebit) 2016-11-26T00:59:32+00:00 Simon Glass sjg@chromium.org 2016-11-13T21:22:16+00:00 e70408c069795fc2084aaee65a1a6c5f42c91a8f This adds support for the Asus Chromebit, and RK3288-based device designed to plug directly into an HDMI monitor. The device tree file comes from Linux v4.8. Signed-off-by: Simon Glass <sjg@chromium.org> 
This adds support for the Asus Chromebit, and RK3288-based device designed
to plug directly into an HDMI monitor. The device tree file comes from
Linux v4.8.

Signed-off-by: Simon Glass <sjg@chromium.org>
rockchip: veyron: Add a note about the SDRAM voltage 2016-11-26T00:59:31+00:00 Simon Glass sjg@chromium.org 2016-11-13T21:22:11+00:00 38ffcb679b1694f8ebf4e5670614fb830ae0c2f2 Add a comment to indicate that we are not supporting the PWM regulator yet. Signed-off-by: Simon Glass <sjg@chromium.org> 
Add a comment to indicate that we are not supporting the PWM regulator
yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
rockchip: Rename jerry files to veyron 2016-11-26T00:59:31+00:00 Simon Glass sjg@chromium.org 2016-11-13T21:22:10+00:00 5e9b15034b9e38a6908610229788cf0746d138fc At present we have a single rk3288-based Chromebook: chromebook_jerry. But all such Chromebooks can use the same binary with only device-tree differences. The family name is 'veyron', so rename the files accordingly. Also update the device-tree filename since this currently differs from Linux. Signed-off-by: Simon Glass <sjg@chromium.org> 
At present we have a single rk3288-based Chromebook: chromebook_jerry. But
all such Chromebooks can use the same binary with only device-tree
differences. The family name is 'veyron', so rename the files accordingly.

Also update the device-tree filename since this currently differs from
Linux.

Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Add support for the samus chromebook 2016-03-17T02:27:27+00:00 Simon Glass sjg@chromium.org 2016-03-16T13:44:43+00:00 374e78efb0c6739c8c700325acca769d7a9e47de This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.

Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard

Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).

The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: Drop all the old pin configuration code 2016-03-17T02:27:25+00:00 Simon Glass sjg@chromium.org 2016-03-12T05:07:15+00:00 779653b0cbe3f634632bc4ecae1ce5df84638326 We don't need this anymore - we can use device tree and the new pinconfig driver instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
We don't need this anymore - we can use device tree and the new pinconfig
driver instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: ivybridge: Move northbridge and PCH init into drivers 2016-01-24T04:08:17+00:00 Simon Glass sjg@chromium.org 2016-01-17T23:11:31+00:00 9ed781a6ffba48d75b3ae0a0058ca439b8e178c2 Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Instead of calling the northbridge and PCH init from bd82x6x_init_extra()
when the PCI bus is probed, call it from the respective drivers. Also drop
the Northbridge init as it has no effect. The registers it touches appear to
be read-only.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: ivybridge: Do not require HAVE_INTEL_ME 2016-01-13T04:20:15+00:00 Bin Meng bmeng.cn@gmail.com 2015-12-11T10:55:49+00:00 fa331fad1eee0bd86470b49a905ed176aa412b9a Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> 
Do not set HAVE_INTEL_ME by default as for some cases Intel ME
firmware even does not reside on the same SPI flash as U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
x86: Remove HAVE_ACPI_RESUME 2015-12-09T09:44:56+00:00 Bin Meng bmeng.cn@gmail.com 2015-11-26T01:46:09+00:00 789fa275b3750e60c60cb3d18eabc9467892c257 These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> 
These are currently dead codes. Until we have complete ACPI support,
we don't know if it works or not. Remove to avoid confusion.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
x86: Remove CPU_INTEL_SOCKET_RPGA989 2015-12-09T09:44:54+00:00 Bin Meng bmeng.cn@gmail.com 2015-11-26T01:46:08+00:00 d475d59020af32bd5b55ca48a5bc73213e53a7c8 This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> 
This Kconfig option name indicates it has something to do with cpu
socket, however it is actually not the case. Remove it and move
options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>