u-boot.git/board/intel, branch v2016.01 Unnamed repository; edit this file 'description' to name the repository. x86: Enable PCIe controller on quark/galileo 2015-09-09T13:48:03+00:00 Bin Meng bmeng.cn@gmail.com 2015-09-03T12:37:25+00:00 316fd3920f67fa8d3ca25a81ceead546464145fa Quark SoC holds the PCIe controller in reset following a power on. U-Boot needs to release the PCIe controller from reset. The PCIe controller (D23:F0/F1) will not be visible in PCI configuration space and any access to its PCI configuration registers will cause system hang while it is held in reset. Enable PCIe controller per Quark firmware writer guide. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> 
Quark SoC holds the PCIe controller in reset following a power on.
U-Boot needs to release the PCIe controller from reset. The PCIe
controller (D23:F0/F1) will not be visible in PCI configuration
space and any access to its PCI configuration registers will cause
system hang while it is held in reset.

Enable PCIe controller per Quark firmware writer guide.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
x86: bayleybay: Convert to use more dm drivers 2015-09-09T13:48:03+00:00 Bin Meng bmeng.cn@gmail.com 2015-08-28T09:22:39+00:00 468e81c405e5d14de4bc7b0d7a4a5540a576a45e Move to driver model for USB and ETH on Intel Bayley Bay. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> 
Move to driver model for USB and ETH on Intel Bayley Bay.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
x86: crownbay: Convert to use CONFIG_DM_ETH for E1000 2015-09-09T13:48:03+00:00 Bin Meng bmeng.cn@gmail.com 2015-08-28T05:25:56+00:00 868767c71a375a07a44cc4fd49d67a4e2b1b9e8b Since E1000 driver has been converted to driver model, enable it on Intel Crown Bay. But the Intel Topcliff GbE driver has not been converted to driver model yet, disable it for now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> 
Since E1000 driver has been converted to driver model, enable it
on Intel Crown Bay. But the Intel Topcliff GbE driver has not been
converted to driver model yet, disable it for now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
x86: crownbay: Enable on-board SMSC superio keyboard controller 2015-08-26T14:54:16+00:00 Bin Meng bmeng.cn@gmail.com 2015-08-24T08:00:08+00:00 4dd02a752c714e1616025fceba78e121807cfc11 So far we only enabled one legacy serial port on the SMSC LPC47m superio chipset on Intel Crown Bay board. As the board also has dual PS/2 ports routed out, enable the keyboard controller which is i8042 compatible so that we can use PS/2 keyboard and mouse. In order to make PS/2 keyboard work with the VGA console, remove CONFIG_VGA_AS_SINGLE_DEVICE. To boot Linux kernel with PIC mode using PIRQ routing table, adjust the mask in the device tree to reserve irq12 which is used by PS/2 mouse. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
So far we only enabled one legacy serial port on the SMSC LPC47m
superio chipset on Intel Crown Bay board. As the board also has
dual PS/2 ports routed out, enable the keyboard controller which
is i8042 compatible so that we can use PS/2 keyboard and mouse.

In order to make PS/2 keyboard work with the VGA console, remove
CONFIG_VGA_AS_SINGLE_DEVICE. To boot Linux kernel with PIC mode
using PIRQ routing table, adjust the mask in the device tree to
reserve irq12 which is used by PS/2 mouse.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
x86: Convert minnowmax to use CONFIG_DM_NET 2015-08-14T15:50:11+00:00 Simon Glass sjg@chromium.org 2015-08-11T04:02:53+00:00 b8098bc1c14ca397291209e0281f0862ddc6f057 Move to driver model for networking on minnowmax. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Move to driver model for networking on minnowmax.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: baytrail: Support operation as an EFI payload 2015-08-05T14:44:08+00:00 Simon Glass sjg@chromium.org 2015-08-04T18:34:02+00:00 b4302582f309b49a08c770960a37af6fe1f3afb3 Disable a few things which interfere with the EFI init. This allows the Minnowboard MAX to boot into EFI, load a U-Boot payload then boot to the U-Boot prompt. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Disable a few things which interfere with the EFI init. This allows the
Minnowboard MAX to boot into EFI, load a U-Boot payload then boot to the
U-Boot prompt.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: Add Intel Bayley Bay board support 2015-08-05T14:42:39+00:00 Bin Meng bmeng.cn@gmail.com 2015-07-30T10:49:17+00:00 9b911bed78c3926fe1129dcc6b0ffbca667dff74 Intel Bayley Bay board is a BayTrail based board. Add this board with existing baytrail fsp support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> 
Intel Bayley Bay board is a BayTrail based board. Add this board
with existing baytrail fsp support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
x86: minnowmax: Remove smsc47x superio codes 2015-08-05T14:42:39+00:00 Bin Meng bmeng.cn@gmail.com 2015-07-30T10:49:14+00:00 456ee909d63a35daa51b70231c4abffa4709e9f3 On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated into the SoC which is enabled by the FSP. Remove the smsc47x superio initialization codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> 
On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated
into the SoC which is enabled by the FSP. Remove the smsc47x superio
initialization codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
x86: minnowmax: initialize the pin-muxing from device tree 2015-06-04T09:32:23+00:00 Gabriel Huau contact@huau-gabriel.fr 2015-05-12T06:18:25+00:00 5d3c2c542dd8878fece0ea96edde125635b492ff Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Simon Glass <sjg@chromium.org> 
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Simon Glass <sjg@chromium.org>
x86: Remove DECLARE_GLOBAL_DATA_PTR in board files 2015-06-04T08:39:38+00:00 Bin Meng bmeng.cn@gmail.com 2015-04-30T11:05:24+00:00 8feb2cc62446fe1de30cb71433ab27917e92e8bd gd is not referenced in those board files so DECLARE_GLOBAL_DATA_PTR should be removed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> 
gd is not referenced in those board files so DECLARE_GLOBAL_DATA_PTR
should be removed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>