<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/board/kosagi, branch v2017.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board/kosagi?h=v2017.01</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/board/kosagi?h=v2017.01'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2016-11-29T15:40:12Z</updated>
<entry>
<title>mx6: ddr: pass mx6_ddr_sysinfo to calibration routines</title>
<updated>2016-11-29T15:40:12Z</updated>
<author>
<name>Eric Nelson</name>
<email>eric@nelint.com</email>
</author>
<published>2016-10-30T23:33:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7f17fb7400ff091dd48f86977655c6a57d06b17c'/>
<id>urn:sha1:7f17fb7400ff091dd48f86977655c6a57d06b17c</id>
<content type='text'>
The DDR calibration routines have scattered support for bus
widths other than 64-bits:

-- The mmdc_do_write_level_calibration() routine assumes the
presence of PHY1, and
-- The mmdc_do_dqs_calibration() routine tries to determine
whether one or two DDR PHYs are active by reading MDCTL.

Since a caller of these routines must have a valid struct mx6_ddr_sysinfo
for use in calling mx6_dram_cfg(), and the bus width is available in the
"dsize" field, use this structure to inform the calibration routines which
PHYs are active.

This allows the use of the DDR calibration routines on CPU variants
like i.MX6SL that only have a single MMDC port.

Signed-off-by: Eric Nelson &lt;eric@nelint.com&gt;
Reviewed-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>treewide: replace #include &lt;asm/errno.h&gt; with &lt;linux/errno.h&gt;</title>
<updated>2016-09-23T21:55:42Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2016-09-21T02:28:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1221ce459d04a428f8880f58581f671b736c3c27'/>
<id>urn:sha1:1221ce459d04a428f8880f58581f671b736c3c27</id>
<content type='text'>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap &lt;asm-generic/errno.h&gt;)

Replace all include directives for &lt;asm/errno.h&gt; with &lt;linux/errno.h&gt;.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>mx6: ddr: Allow changing REFSEL and REFR fields</title>
<updated>2016-09-06T16:22:48Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2016-08-29T23:37:15Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=edf0093732225c2fd0791c3864e9a3eef1f92f19'/>
<id>urn:sha1:edf0093732225c2fd0791c3864e9a3eef1f92f19</id>
<content type='text'>
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.

Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:

$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4      0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800

So introduce a mechanism for users to be able to configure
REFSEL and REFR fields as needed.

Keep all the mx6 SPL users in their current REF_SEL and REFR values,
so no functional changes for the existing users.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Reviewed-by: Eric Nelson &lt;eric@nelint.com&gt;
</content>
</entry>
<entry>
<title>arm: imx6: Enable DDR calibration on Novena</title>
<updated>2016-02-02T19:59:05Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2015-12-16T14:40:07Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=89d485940106c095ec69ecb12a78a42e096dece7'/>
<id>urn:sha1:89d485940106c095ec69ecb12a78a42e096dece7</id>
<content type='text'>
Enable the DDR calibration functionality on Novena to deal with the
memory SoDIMM on this board. Moreover, tweak the initial DDR DRAM
parameters so the calibration works properly.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: imx6: novena, gw_ventana: Fix use of pfuze100 bit definitions</title>
<updated>2015-12-01T15:09:51Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2015-11-26T13:08:50Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=18e02ffe5e626fe409ca9427e368c879f6ee450c'/>
<id>urn:sha1:18e02ffe5e626fe409ca9427e368c879f6ee450c</id>
<content type='text'>
The following patch changed the PFUZE100 swbst register bit definitions
and broke PMIC configuration on multiple boards, at least on the novena
and gw_ventana. This patch fixes it.

commit 8fa46350a4c7dca7710362f6c871098557b934ad
Author: Peng Fan &lt;Peng.Fan@freescale.com&gt;
Date:   Fri Aug 7 16:43:45 2015 +0800

    power: regulator: add pfuze100 support

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Cc: Peng Fan &lt;Peng.Fan@freescale.com&gt;
Cc: Przemyslaw Marczak &lt;p.marczak@samsung.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Tim Harvey &lt;tharvey@gateworks.com&gt;
Cc: Vagrant Cascadian &lt;vagrant@aikidev.net&gt;
Reviewed-by: Przemyslaw Marczak &lt;p.marczak@samsung.com&gt;
Tested-by: Vagrant Cascadian &lt;vagrant@aikidev.net&gt;
Reviewed-by: Peng Fan &lt;Peng.Fan@freescale.com&gt;
Acked-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
</content>
</entry>
<entry>
<title>input: Support the German keymap</title>
<updated>2015-11-20T03:13:41Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-11-11T17:05:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b1d7a1875e2f96417a2ecd7ebe1680f650c2be22'/>
<id>urn:sha1:b1d7a1875e2f96417a2ecd7ebe1680f650c2be22</id>
<content type='text'>
Add support for the German keymap, taken from i8042.c. This can be selected
when the input library it initialised.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>input: Add the keycode translation tables separately</title>
<updated>2015-11-20T03:13:40Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-10-19T03:17:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=66877b0f5fc96906d70f1264b3b8102d2156360f'/>
<id>urn:sha1:66877b0f5fc96906d70f1264b3b8102d2156360f</id>
<content type='text'>
Require the caller to add the keycode translation tables separately so that
it can select which ones to use. In a later patch we will add the option to
add German tables.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>novena: Remove empty reset_cpu()</title>
<updated>2015-11-12T16:26:33Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2015-11-03T00:21:34Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=115866c599d7efd54a7c24c7ab288b30e082ba5d'/>
<id>urn:sha1:115866c599d7efd54a7c24c7ab288b30e082ba5d</id>
<content type='text'>
There is really no need to provide an empty reset_cpu() implementation,
so just remove it.

Cc: Marek Vasut &lt;marex@denx.de&gt;
Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>video: Drop DEV_FLAGS_SYSTEM flag</title>
<updated>2015-11-05T07:22:21Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-11-04T07:23:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1caf934a0504013874238445daaea7f32c36ab04'/>
<id>urn:sha1:1caf934a0504013874238445daaea7f32c36ab04</id>
<content type='text'>
DEV_FLAGS_SYSTEM does not have any actual meaning, hence drop it.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>mx6: remove SYS_SOC from board Kconfig</title>
<updated>2015-09-13T08:37:29Z</updated>
<author>
<name>Peng Fan</name>
<email>Peng.Fan@freescale.com</email>
</author>
<published>2015-09-07T06:59:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f20562e4c40adc3a16cfce4d7715e77969eccd0a'/>
<id>urn:sha1:f20562e4c40adc3a16cfce4d7715e77969eccd0a</id>
<content type='text'>
Remove duplicated SYS_SOC Kconfig entry from board Kconfig,
because we have this entry in arch/arm/cpu/armv7/mx6/Kconfig.

Signed-off-by: Peng Fan &lt;Peng.Fan@freescale.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Heiko Schocher &lt;hs@denx.de&gt;
Cc: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Troy Kisky &lt;troy.kisky@boundarydevices.com&gt;
Cc: Nikita Kiryanov &lt;nikita@compulab.co.il&gt;
Cc: "Eric Bénard" &lt;eric@eukrea.com&gt;
Cc: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Cc: Tim Harvey &lt;tharvey@gateworks.com&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Markus Niebel &lt;Markus.Niebel@tq-group.com&gt;
Cc: Otavio Salvador &lt;otavio@ossystems.com.br&gt;
Acked-by: Stefan Roese &lt;sr@denx.de&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
Acked-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
Acked-by: Markus Niebel &lt;Markus.Niebel@tq-group.com&gt;
Acked-by: Troy Kisky &lt;troy.kisky@boundarydevices.com&gt;
Acked-by: Igor Grinberg &lt;grinberg@compulab.co.il&gt;
</content>
</entry>
</feed>
