u-boot.git/board/maxbcm, branch v2016.01

arm: mvebu: Move Armada XP/38x Kconfig to mach specific Kconfig file

2015-10-20T05:12:44+00:00

Introduce a mach-mvebu/Kconfig for all Armada based SoC's.

Signed-off-by: Stefan Roese

arm: mvebu: serdes: Move Armada XP SERDES / PHY init code into new directory

2015-07-23T08:38:05+00:00

With the upcoming addition of the Armada 38x SPL support, which is not
compatible to the Armada XP SERDES init code, we need to introduce a new
directory infrastructure. So lets move the AXP serdes init code into
a new directory. This way the A38x code can be added in a clean way.

Signed-off-by: Stefan Roese

arm: mvebu: Move mvebu-common into mach-mvebu

2015-05-05T12:28:29+00:00

Now that the mach-mvebu directory exists and is used by Armada XP we can
move the mvebu-common files into this directory as well.

Signed-off-by: Stefan Roese 
Cc: Masahiro Yamada 
Tested-by: Kevin Smith 
Tested-by: Dirk Eibach

arm: armada-xp: Move SoC headers to mach-mvebu/include/mach

2015-05-05T12:28:29+00:00

Move arch/arm/include/asm/arch-armada-xp/*
     -> arch/arm/mach-mvebu/include/mach/*

Additionally the SYS_SOC is renamed from "armada-xp" to "mvebu". With this
change all these files can better be shared with other, newer Mavell
MVEBU SoC's. Like the upcoming Armada 38x support.

Signed-off-by: Stefan Roese 
Cc: Masahiro Yamada 
Tested-by: Kevin Smith 
Tested-by: Dirk Eibach

arm: mvebu: maxbcm: Fix compilation warning and add Spansion SPI NOR support

2015-02-06T16:25:08+00:00

This patch fixes the following compilation warning for maxbcm:

Building maxbcm board...
   text    data     bss     dec     hex filename
 160075    6596   38240  204911   3206f ./u-boot
board/maxbcm/maxbcm.c: In function 'reset_phy':
board/maxbcm/maxbcm.c:68:6: warning: unused variable 'reg' [-Wunused-variable]
  u16 reg;
      ^
board/maxbcm/maxbcm.c:66:6: warning: unused variable 'devadr' [-Wunused-variable]
  u16 devadr = CONFIG_PHY_BASE_ADDR;
      ^

Additionally support Spansion SPI NOR flash is added. With larger SPI device
support via the CONFIG_SPI_FLASH_BAR define.

Signed-off-by: Stefan Roese 
Reviewed-by: Luka Perkov

arm: maxbcm: Enable SPL to include DDR training code into U-Boot

2015-02-06T16:24:43+00:00

This patch adds SPL support to the maxbcm MV78460 based board. Including
the fixed DDR configuratrion needed for the DDR training code. And the
the serdes PHY init code.

Signed-off-by: Stefan Roese 
Reviewed-by: Luka Perkov

arm: mvebu: Placeholder bin_hdr file can now be removed

2015-02-06T16:24:41+00:00

With this patchset the Marvell bin_hdr (DDR training) code is intergrated
into mainline U-Boot. We can remove the placeholder file again, which was
only introduced to make U-Boot compile and link again.

Signed-off-by: Stefan Roese 
Reviewed-by: Luka Perkov

kconfig: arm: select CPU_V7 for some new boards

2014-11-13T13:37:18+00:00

This commit adds "select CPU_V7" for some new boards that were not
covered by commit 2e07c249a67e
(kconfig: arm: introduce symbol for ARM CPUs).

Redundant "SYS_CPU" defines and "string" directives should be removed.

Signed-off-by: Masahiro Yamada 
Acked-by: Stefan Roese 
Acked-by: Georges Savoundararadj

arm: db-mv784mp-gp/maxbcm Add placeholder bin_hdr file so that linking works

2014-10-27T21:54:12+00:00

This file should contain the bin_hdr generated by the original Marvell
U-Boot implementation. As this is currently not included in this
U-Boot version, we have added this placeholder, so that the U-Boot
image can be generated without errors.

If you have a known to be working bin_hdr for your board, then you
just need to replace this text file here with the binary header
and recompile U-Boot.

In a few weeks, mainline U-Boot will get support to generate the
bin_hdr with the DDR training code itself. By implementing this code
as SPL U-Boot. Then this file will not be needed any more and will
get removed.

Signed-off-by: Stefan Roese

arm: armada-xp: Add basic support for the maxBCM board

2014-10-23T13:59:21+00:00

The maxBCM board is equipped with the Marvell Armada-XP MV78460 SoC. It
integrates an SPI NOR flash and an Marvell 88E6185 switch.

Signed-off-by: Stefan Roese