Per AN3221 (MPC5200B SDRAM Initialization and Configuration), the SDelay
register must be written a value of 0x00000004 as the first step of the
SDRAM contorller configuration.

Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>

Affects boards: icecube (lite5200), jupiter, motionpro, tqm5200

Tested on: lite5200b

Note: the fixup functions have not been moved to a common place.  This
patch is targeted for immediate merging as in solves a build issue, but
the final name/location of the fixups is still subject to debate.  I
propose to merge this now, and move the fixups in the next merge window
to be usable by all targets.

Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>

After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which
networking does not function. This commit switches PHY to TX mode by clearing
the FX_SEL bit of Mode Control Register. It also reverses commit
008861a2f3ef2c062744d733787c7e530a1b8761, i.e., a temporary workaround.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>

Signed-off-by: Jan Wrobel <wrr@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>

Signed-off-by: Jan Wrobel <wrr@semihalf.com>
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>

to allow booting of FDT-expecting kernels.