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<title>u-boot.git/board/nvidia/dalmore, branch v2014.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board/nvidia/dalmore?h=v2014.07</id>
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<updated>2014-04-17T15:41:06Z</updated>
<entry>
<title>ARM: tegra: Tegra114 pinmux cleanup</title>
<updated>2014-04-17T15:41:06Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2014-03-21T18:29:00Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1fa3a634137c9f40b207cff1079fe0dfbd9b3378'/>
<id>urn:sha1:1fa3a634137c9f40b207cff1079fe0dfbd9b3378</id>
<content type='text'>
This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.

The entries in tegra114_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

This introduces a few changes to pin/group/function naming and the set of
available functions for each pin. The new values now exactly match the
TRM; the chip documentation. I adjusted a few entries in
pinmux-config-dalmore.h due to this.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: pinmux naming consistency fixes</title>
<updated>2014-04-17T15:41:05Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2014-03-21T18:28:56Z</published>
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<id>urn:sha1:dfb42fc95df6b5908fb593db9132018233430fe9</id>
<content type='text'>
Clean up the naming of pinmux-related objects:
* Refer to drive groups rather than pad groups to match the Linux kernel.
* Ensure all pinmux API types are prefixed with pmux_, values (defines)
  are prefixed with PMUX_, and functions prefixed with pinmux_.
* Modify a few type names to make their content clearer.
* Minimal changes to SoC-specific .h/.c files are made so the code still
  compiles. A separate per-SoC change will be made immediately following,
  in order to keep individual patch size down.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: make all I2C ports open-drain</title>
<updated>2014-03-26T22:20:56Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2014-03-12T19:10:44Z</published>
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<id>urn:sha1:352580870ca64b23a485a6b2ba6febc240b10904</id>
<content type='text'>
I2C protocol requires open-drain IOs. Fix the Dalmore and Venice2 pinmux
tables to configure the IOs correctly. Without this, Tegra may actively
drive the lines high while an external device is actively driving the
lines low, which can only lead to bad things.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>board: arm: convert makefiles to Kbuild style</title>
<updated>2013-11-01T15:42:12Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2013-10-21T02:53:37Z</published>
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<id>urn:sha1:a79854a90f7297ddfda2114c867fd62643fa6e3a</id>
<content type='text'>
Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Cc: Albert ARIBAUD &lt;albert.u.boot@aribaud.net&gt;
Cc: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Prafulla Wadaskar &lt;prafulla@marvell.com&gt;
Cc: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Cc: Vipin Kumar &lt;vipin.kumar@st.com&gt;
Cc: Tom Warren &lt;twarren@nvidia.com&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>Tegra114: MMC: Add SD bus power-rail init routine</title>
<updated>2013-03-25T16:56:07Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2013-03-18T21:51:20Z</published>
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<id>urn:sha1:6d9ea159e4900dc6bc4b38a064fc87cba4582c09</id>
<content type='text'>
T114 requires SD bus power-rail bringup for the SDIO card on SDMMC3.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Tegra114: Dalmore: Add SDIO3 pad config to pinctrl_config table</title>
<updated>2013-03-25T16:56:07Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2013-03-18T21:47:55Z</published>
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<id>urn:sha1:2a04a317911a550e55c2943d59063b621ea5f4ee</id>
<content type='text'>
SDIO1 (the SD-card slot on Dalmore) needs to have its pads setup
before the MMC driver is added.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Tegra114: Dalmore: Add pad config tables/code based on pinmux code</title>
<updated>2013-03-14T18:49:14Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2013-03-11T23:43:49Z</published>
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<id>urn:sha1:477393e7875cf4261f107fdfb8887309ea7fc3f7</id>
<content type='text'>
Pad config registers exist in APB_MISC_GP space, and control slew
rate, drive strengh, schmidt, high-speed, and low-power modes for
all of the pingroups in Tegra30. This builds off of the pinmux
way of constructing init tables to configure select pads (SDIOCFG,
for instance) during pinmux_init().

Currently, no padcfg entries exist. SDIO3CFG will be added when the
MMC driver is added as per the TRM to work with the SD-card slot on
Dalmore E1611.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Tegra114: Dalmore: Always use DEFAULT instead of DISABLE for lock bits</title>
<updated>2013-03-14T18:48:55Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2013-03-13T22:40:33Z</published>
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<id>urn:sha1:f31a5443a8b52a613fcafc0330a303420eafcca4</id>
<content type='text'>
The pinmux code issues a warning if the caller attempts to disable the
lock bit in a pinmux register, since this is impossible (once it's
locked, the only way to unlock it is to reset the device/pmt controller).

The I2C/DDC/CEC/USB macros expect a lock setting to be passed in,
and the previous setting of DISABLE caused the pinmux table parsing
code to issue the warning. Changing the lock bits in these table
entries to DEFAULT (i.e. don't touch it) fixes this.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Tegra114: pinmux: Update pinmux tables &amp; code, fix a bug w/SDMMC3 init</title>
<updated>2013-03-14T18:06:43Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2013-03-01T21:38:20Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8b7776b9f95d542d0e81357c4f8aa32f7bf466e5'/>
<id>urn:sha1:8b7776b9f95d542d0e81357c4f8aa32f7bf466e5</id>
<content type='text'>
Use the latest tables &amp; code from our internal U-Boot repo.
The SDMMC3_CD, CLK_LB_IN and CLK_LB_OUT offsets in the pingroup
table were off by a few indices, causing the pinmux init code to
write bad data to the PINMUX_AUX_ regs. This also enabled the lock
bit, which made it impossible to reconfig the pads correctly for
SDMMC3 (SD card on Dalmore) operation. Also fixes SPI_CS2_N,
USB_VBUS_EN0, HDMI_CEC and UART2_RXD/TXD muxes.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Tegra114: Add/enable Dalmore build (T114 reference board)</title>
<updated>2013-02-11T17:35:26Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren.nvidia@gmail.com</email>
</author>
<published>2013-01-28T13:32:13Z</published>
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<id>urn:sha1:07067145dee374e970ffc033cff76982e8cf2e19</id>
<content type='text'>
This build is stripped down. It boots to the command prompt.
GPIO is the only peripheral supported. Others TBD.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
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