u-boot.git/board/nvidia, branch v2013.01 Unnamed repository; edit this file 'description' to name the repository. ARM: tegra: enable 8-bit SD slots in board files 2012-11-19T15:15:42+00:00 Stephen Warren swarren@nvidia.com 2012-11-02T06:56:13+00:00 72573543b5b9f788b46fb9e7ab3372cfeba8d25f Harmony contains an SD slot with all 8 bits routed. This allows plugging in an eMMC-chip-in-SD-form-factor. Seaboard/Springbank/Ventana/AC100 all have an eMMC chip with all 8 bits hooked up. Now that the U-Boot eMMC code fully supports 8-bit operation, initialize those ports as 8-bit instead of 4-bit to improve performance. Whistler was already registering its ports as 8-bit. TrimSlice doesn't have any 8-bit ports. I don't have any Avionic Design boards nor the Colibri board to test with. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> 
Harmony contains an SD slot with all 8 bits routed. This allows plugging
in an eMMC-chip-in-SD-form-factor.

Seaboard/Springbank/Ventana/AC100 all have an eMMC chip with all 8 bits
hooked up.

Now that the U-Boot eMMC code fully supports 8-bit operation, initialize
those ports as 8-bit instead of 4-bit to improve performance.

Whistler was already registering its ports as 8-bit.

TrimSlice doesn't have any 8-bit ports.

I don't have any Avionic Design boards nor the Colibri board to test with.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
tegra: fdt: Add LCD definitions for Seaboard 2012-11-19T15:15:39+00:00 Simon Glass sjg@chromium.org 2012-10-17T13:24:58+00:00 77139f5170ca74a7724f773ac8b355f8e191576c The Seaboard has a 1366x768 16bpp LCD. The backlight is controlled by one of the PWMs. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> 
The Seaboard has a 1366x768 16bpp LCD. The backlight is controlled
by one of the PWMs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
tegra: Add LCD support to Nvidia boards 2012-11-19T15:15:37+00:00 Simon Glass sjg@chromium.org 2012-10-17T13:24:52+00:00 1b24a50b44d9577c65759d252571f94e8f702777 Add calls to the LCD driver from Nvidia board code. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> 
Add calls to the LCD driver from Nvidia board code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
tegra: Add support for PWM 2012-11-19T15:15:36+00:00 Simon Glass sjg@chromium.org 2012-10-17T13:24:49+00:00 e1ae0d1f7185948d576dd7b53654444a0079a92d The pulse width/frequency modulation peripheral supports generating a repeating pulse. It is useful for controlling LCD brightness. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> 
The pulse width/frequency modulation peripheral supports generating
a repeating pulse. It is useful for controlling LCD brightness.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
ARM: tegra: don't request GPIO from Seaboard's SPL 2012-10-29T16:07:05+00:00 Stephen Warren swarren@nvidia.com 2012-10-22T06:19:36+00:00 a2ab6b7d320423ab4d925d75c588c2a13fce61c6 Seaboard has a GPIO that switches an external mux between Tegra's debug UART and SPI flash. This is initialized from the SPL so that SPL debug output can be seen. Simplify the code that does this, and don't actually request the GPIO in the SPL; just program it. This saves ~4.5K from the size of the SPL, mostly BSS due to the large gpio_names[] table that is no longer required. This makes Seaboard's SPL fit within the current max size. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Allen Martin <amartin@nvidia.com> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> 
Seaboard has a GPIO that switches an external mux between Tegra's debug
UART and SPI flash. This is initialized from the SPL so that SPL debug
output can be seen. Simplify the code that does this, and don't actually
request the GPIO in the SPL; just program it. This saves ~4.5K from the
size of the SPL, mostly BSS due to the large gpio_names[] table that is
no longer required. This makes Seaboard's SPL fit within the current max
size.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Allen Martin <amartin@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
ARM: tegra: select between Seaboard/Ventana at compile time 2012-10-29T16:07:05+00:00 Stephen Warren swarren@nvidia.com 2012-10-22T06:19:35+00:00 da1f735272aaccf201b7d289c86fe8c6ff848f4f Seaboard and Ventana are very similar boards, and so share the seaboard.c board file. The one difference needed so far is detected at run-time by calling machine_is_ventana(). This bloats the Ventana build with code that is never used. Switch to detecting Ventana at compile time to remove bloat. This shaves ~5K off the SPL size on Ventana, and makes the SPL fit within the max size. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> 
Seaboard and Ventana are very similar boards, and so share the seaboard.c
board file. The one difference needed so far is detected at run-time by
calling machine_is_ventana(). This bloats the Ventana build with code
that is never used. Switch to detecting Ventana at compile time to remove
bloat. This shaves ~5K off the SPL size on Ventana, and makes the SPL fit
within the max size.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
ARM: tegra: Whistler: remove unused USB alias 2012-10-29T16:07:05+00:00 Stephen Warren swarren@nvidia.com 2012-10-12T09:45:50+00:00 56f42f85f5a14040fb0e74fd6cad3910643830d6 Port USB1 on Whistler is intended as a device port for USB recovery. Whistler's DT currently contains an alias for this USB port, even though Whistler's config doesn't enable multiple USB controllers, so the alias is unused. Remove the unused alias for consistency for now. Similar, explicitly disable the port in the device tree too. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> 
Port USB1 on Whistler is intended as a device port for USB recovery.
Whistler's DT currently contains an alias for this USB port, even though
Whistler's config doesn't enable multiple USB controllers, so the alias
is unused. Remove the unused alias for consistency for now. Similar,
explicitly disable the port in the device tree too.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
ARM: tegra: Harmony: enable ULPI USB port 2012-10-29T16:07:04+00:00 Stephen Warren swarren@nvidia.com 2012-10-12T09:45:48+00:00 699c40e8789cfbb5c3ca4ef2849a4bd051ff79bb The ULPI port is routed onto pins on the mini PCI Express connector. A standard breakout board may be used to access the port. * Add required DT entries to configure the ULPI port. * Setup up the ULPI pinmux in the board code. * Enable multiple USB controller and ULPI support in the board config. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> 
The ULPI port is routed onto pins on the mini PCI Express connector. A
standard breakout board may be used to access the port.

* Add required DT entries to configure the ULPI port.
* Setup up the ULPI pinmux in the board code.
* Enable multiple USB controller and ULPI support in the board config.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
tegra: move common features to a common makefile 2012-10-29T16:07:04+00:00 Marc Dietrich marvin24@gmx.de 2012-10-03T04:26:28+00:00 73286d8729c0a2325911719492218477caa2c58e For Non-Nvidia boards to include newly added features (like emc clock scaling) it would be necessary to add each feature to their own board Makefile. This is because currently the top Makefile automaticly includes these features only for Nvidia boards. This patch adds a simple Makefile include so all new features become available for non-Nvidia board vendors. Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Thierry Reding <thierry.reding@avionic-design.de> Cc: Lucas Stach <dev@lynxeye.de> Signed-off-by: Marc Dietrich <marvin24@gmx.de> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com> 
For Non-Nvidia boards to include newly added features (like emc clock
scaling) it would be necessary to add each feature to their own board
Makefile. This is because currently the top Makefile automaticly includes
these features only for Nvidia boards.

This patch adds a simple Makefile include so all new features become
available for non-Nvidia board vendors.

Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Thierry Reding <thierry.reding@avionic-design.de>
Cc: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
tegra: nand: add board pinmux 2012-10-15T18:54:07+00:00 Lucas Stach dev@lynxeye.de 2012-09-29T10:02:09+00:00 c0720afbb56f91fd33fb5b4e564e1037809c6304 Boards may require a different pinmux setup for NAND than the default one. Add a way to call into board specific code to set this up. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Tom Warren <twarren@nvidia.com> 
Boards may require a different pinmux setup for NAND than the default one.
Add a way to call into board specific code to set this up.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>