u-boot.git/board/phytec/common, branch next Unnamed repository; edit this file 'description' to name the repository. board: phytec: phycore-imx91-93: Add phyCORE-i.MX91 support 2026-04-02T12:05:23+00:00 Primoz Fiser primoz.fiser@norik.com 2026-03-17T12:31:26+00:00 77801f4b644b61e8a626a8a07b8249b8d29b118b As the PHYTEC phyCORE-i.MX91 [1] is just another variant of the existing PHYTEC phyCORE-i.MX93 SoM but with i.MX91 SoC populated instead, add it to the existing board-code "phycore_imx93", and rename that board to "phycore_imx91_93" to reflect the dual SoCs support. While at it, also rename and change common files accordingly. This way i.MX91 and i.MX93 SoC variants of the phyCORE SoM share most of the code and documentation without duplication, while maintaining own device-tree and defconfigs for each CPU variant. Supported features: - 1GB LPDDR4 RAM - Debug UART - EEPROM - eMMC - Ethernet - SD-card - USB Product page SoM: [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> 
As the PHYTEC phyCORE-i.MX91 [1] is just another variant of the existing
PHYTEC phyCORE-i.MX93 SoM but with i.MX91 SoC populated instead, add it
to the existing board-code "phycore_imx93", and rename that board to
"phycore_imx91_93" to reflect the dual SoCs support. While at it, also
rename and change common files accordingly. This way i.MX91 and i.MX93
SoC variants of the phyCORE SoM share most of the code and documentation
without duplication, while maintaining own device-tree and defconfigs
for each CPU variant.

Supported features:
 - 1GB LPDDR4 RAM
 - Debug UART
 - EEPROM
 - eMMC
 - Ethernet
 - SD-card
 - USB

Product page SoM:
[1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
board: phytec: phytec_som_detection: Add support for phyFLEX 2025-12-07T14:07:07+00:00 Daniel Schultz d.schultz@phytec.de 2025-11-24T08:25:06+00:00 7bcf0160901970f4417488982199fece129567b4 phyFLEX are SoMs based on the FPSC standard. Add additional "SOM types" for the phyFLEX modules base on the FPSC Gamma specification. These modules come in four different variants; prototypes (PT), standard product (SP), KSP (KP) and KSM (KM). Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Teresa Remmet <t.remmet@phytec.de> Tested-by: Dominik Haller <d.haller@phytec.de> 
phyFLEX are SoMs based on the FPSC standard.

Add additional "SOM types" for the phyFLEX modules base on the
FPSC Gamma specification. These modules come in four different
variants; prototypes (PT), standard product (SP), KSP (KP) and
KSM (KM).

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
Tested-by: Dominik Haller <d.haller@phytec.de>
board: phytec: phytec_som_detection: Add missing assignment 2025-12-07T14:07:07+00:00 Daniel Schultz d.schultz@phytec.de 2025-11-24T08:25:05+00:00 9ce3d264e3b79b91d997eaa89dcd51488259c2b9 Assign the return value of snprintf (total length) to a variable to properly check if the string has the correct length. Currently, this variable is always zero and the length check after snprintf will always fail. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> 
Assign the return value of snprintf (total length) to a variable to
properly check if the string has the correct length.

Currently, this variable is always zero and the length check after
snprintf will always fail.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Merge tag 'u-boot-socfpga-next-20250930' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next 2025-09-30T22:11:23+00:00 Tom Rini trini@konsulko.com 2025-09-30T22:11:23+00:00 aff68c8514858ddd8d2e508d47bede566511521b SoCFPGA updates for v2025.10: CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762 This pull request brings a set of updates across SoCFPGA platforms covering Agilex5, Agilex7, N5X, and Stratix10. The changes include: * Agilex5 enhancements: - USB3.1 enablement and DWC3 host driver support - System Manager register configuration for USB3 - Watchdog timeout increase and SDMMC clock API integration - dcache handling improvements in SMC mailbox path - Enable SPL_SYS_DCACHE_OFF in defconfig * Clock driver improvements: - Introduce dt-bindings header for Agilex clocks - Add enable/disable API and EMAC clock selection fixes - Replace manual shifts with FIELD_GET usage * DDR updates: - IOSSM mailbox compatibility check - Correct DDR calibration status handling * Device tree changes: - Agilex5: disable cache allocation for reads - Stratix10: add NAND IP node - Enable driver model watchdog - Enable USB3.1 node for Agilex5 * Config cleanups: - Simplify Agilex7 VAB defconfig - Remove obsolete SYS_BOOTM_LEN from N5X VAB config - Enable CRC32 support for SoCFPGA - Increase USB hub debounce timeout Overall this set improves reliability of DDR and cache flows, adds missing USB and MMC features for Agilex5, and refines clock and configuration handling across platforms. This patch set has been tested on Agilex 5 devkit, and Agilex devkit. 
SoCFPGA updates for v2025.10:

CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762

This pull request brings a set of updates across SoCFPGA platforms
covering Agilex5, Agilex7, N5X, and Stratix10. The changes include:

* Agilex5 enhancements:
  - USB3.1 enablement and DWC3 host driver support
  - System Manager register configuration for USB3
  - Watchdog timeout increase and SDMMC clock API integration
  - dcache handling improvements in SMC mailbox path
  - Enable SPL_SYS_DCACHE_OFF in defconfig

* Clock driver improvements:
  - Introduce dt-bindings header for Agilex clocks
  - Add enable/disable API and EMAC clock selection fixes
  - Replace manual shifts with FIELD_GET usage

* DDR updates:
  - IOSSM mailbox compatibility check
  - Correct DDR calibration status handling

* Device tree changes:
  - Agilex5: disable cache allocation for reads
  - Stratix10: add NAND IP node
  - Enable driver model watchdog
  - Enable USB3.1 node for Agilex5

* Config cleanups:
  - Simplify Agilex7 VAB defconfig
  - Remove obsolete SYS_BOOTM_LEN from N5X VAB config
  - Enable CRC32 support for SoCFPGA
  - Increase USB hub debounce timeout

Overall this set improves reliability of DDR and cache flows,
adds missing USB and MMC features for Agilex5, and refines clock
and configuration handling across platforms.

This patch set has been tested on Agilex 5 devkit, and Agilex devkit.
board: phytec: common: Fix missing newline in error message 2025-09-24T13:50:13+00:00 Wadim Egorov w.egorov@phytec.de 2025-09-19T06:39:48+00:00 96971e5090cd6975023d0556b3d47b195442902e The error message in phytec_get_product_name() was missing a newline, causing log output to be concatenated with subsequent messages. Add the newline to improve readability. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> 
The error message in phytec_get_product_name() was missing a newline,
causing log output to be concatenated with subsequent messages. Add
the newline to improve readability.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Merge patch series "Update SoM detection related code and configs" 2025-08-26T20:37:02+00:00 Tom Rini trini@konsulko.com 2025-08-26T18:49:35+00:00 b4ae2926068a96264a88311647189dd8dcf28585 Wadim Egorov <w.egorov@phytec.de> says: Update Kconfig options for phyCORE-AM62Ax to align with other boards and prepare common board code for the upcoming phyCORE-AM62L which has the SoM EEPROM connected on a different bus. Link: https://lore.kernel.org/r/20250815111051.2277173-1-w.egorov@phytec.de 
Wadim Egorov <w.egorov@phytec.de> says:

Update Kconfig options for phyCORE-AM62Ax to align with other boards and
prepare common board code for the upcoming phyCORE-AM62L which has the
SoM EEPROM connected on a different bus.

Link: https://lore.kernel.org/r/20250815111051.2277173-1-w.egorov@phytec.de
board: phytec: phycore-am62a: Update SoM detection Kconfig options 2025-08-26T18:49:21+00:00 Wadim Egorov w.egorov@phytec.de 2025-08-15T11:10:50+00:00 9cf4f522fc96e29df4ab23f5bcbbbe432ae32237 Drop SUPPORT_EXTENSION_SCAN and enable PHYTEC_SOM_DETECTION_BLOCKS to align with other PHYTEC platforms. These options were missed when phyCORE-AM62Ax support was added. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> 
Drop SUPPORT_EXTENSION_SCAN and enable PHYTEC_SOM_DETECTION_BLOCKS
to align with other PHYTEC platforms. These options were missed when
phyCORE-AM62Ax support was added.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
board: phytec: common: k3: Use CONFIG_PHYTEC_EEPROM_BUS 2025-08-26T18:49:20+00:00 Dominik Haller d.haller@phytec.de 2025-08-15T11:10:49+00:00 437f663e6c35bb210a115bbbd295efbd9d9c54a1 Use CONFIG_PHYTEC_EEPROM_BUS instead of the hard coded value for the i2c bus. Signed-off-by: Dominik Haller <d.haller@phytec.de> Signed-off-by: Wadim Egorov <w.egorov@phytec.de> 
Use CONFIG_PHYTEC_EEPROM_BUS instead of the hard coded value for the i2c bus.

Signed-off-by: Dominik Haller <d.haller@phytec.de>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
board: phytec: common: Add PHYTEC_EEPROM_BUS to Kconfig 2025-08-26T18:49:20+00:00 Dominik Haller d.haller@phytec.de 2025-08-15T11:10:48+00:00 88a1816a9b4ef6a202a832c7f59099ddae903e6b Add the option to choose a different bus number than 0 for the i2c eeprom based som detection. Signed-off-by: Dominik Haller <d.haller@phytec.de> Signed-off-by: Wadim Egorov <w.egorov@phytec.de> 
Add the option to choose a different bus number than 0 for the i2c eeprom
based som detection.

Signed-off-by: Dominik Haller <d.haller@phytec.de>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
board: phytec: common: k3: Making setup_mac_from_eeprom optional 2025-08-21T16:02:49+00:00 John Ma jma@phytec.com 2025-08-13T21:31:16+00:00 29ce50acbb40d64aabf789640a2866a9f71aefa6 Making the setup_mac_from_eeprom optional for boards without CONFIG_PHYTEC_SOM_DETECTION_BLOCKS. Signed-off-by: John Ma <jma@phytec.com> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> 
Making the setup_mac_from_eeprom optional for boards without
CONFIG_PHYTEC_SOM_DETECTION_BLOCKS.

Signed-off-by: John Ma <jma@phytec.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>