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<title>u-boot.git/board/phytec/common, branch v2025.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board/phytec/common?h=v2025.04</id>
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<updated>2025-01-31T17:08:04Z</updated>
<entry>
<title>board: phytec: common: k3: Expose product infos to Linux</title>
<updated>2025-01-31T17:08:04Z</updated>
<author>
<name>Daniel Schultz</name>
<email>d.schultz@phytec.de</email>
</author>
<published>2025-01-23T14:43:50Z</published>
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<id>urn:sha1:058ed281faed1bac6005d3ebc126fae825309158</id>
<content type='text'>
Call 'phytec_ft_board_fixup' in the common K3 board code
to expose the product name and part number to Linux.

Signed-off-by: Daniel Schultz &lt;d.schultz@phytec.de&gt;
Reviewed-by: Wadim Egorov &lt;w.egorov@phytec.de&gt;
</content>
</entry>
<entry>
<title>board: phytec: common: Add product information to FTD</title>
<updated>2025-01-31T17:08:04Z</updated>
<author>
<name>Daniel Schultz</name>
<email>d.schultz@phytec.de</email>
</author>
<published>2025-01-23T14:43:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9c46b8c4e075fb093642e0fc692c16833647a912'/>
<id>urn:sha1:9c46b8c4e075fb093642e0fc692c16833647a912</id>
<content type='text'>
ft_board_setup inside the board code allows to alter
device-tree during the boot process.

Introduce a new function for the PHYTEC SOM detection
to read the product name and part number from the EEPROM
content and include both into the device-tree as
* phytec,som-part-number
* phytec,som-product-name

This function can be called from the board code when those
values should be exposed to Linux.

This patch also updates the phytec_print_som_info
function and changes the output.

Signed-off-by: Daniel Schultz &lt;d.schultz@phytec.de&gt;
Reviewed-by: Wadim Egorov &lt;w.egorov@phytec.de&gt;
Tested-by: Wadim Egorov &lt;w.egorov@phytec.de&gt;
</content>
</entry>
<entry>
<title>board: phytec: common: k3: Add missing boot source to env</title>
<updated>2025-01-23T18:11:50Z</updated>
<author>
<name>Daniel Schultz</name>
<email>d.schultz@phytec.de</email>
</author>
<published>2025-01-16T11:29:29Z</published>
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<id>urn:sha1:b2a04cd075c044df22dc1e7a90b7c38d6b3d888f</id>
<content type='text'>
We set the boot source as environment variable 'boot'.
Also include 'uart' and 'usbdfu' as possible boot sources.

Signed-off-by: Daniel Schultz &lt;d.schultz@phytec.de&gt;
Reviewed-by: Wadim Egorov &lt;w.egorov@phytec.de&gt;
</content>
</entry>
<entry>
<title>Merge patch series "Add phyCORE AM62Ax"</title>
<updated>2024-12-14T02:09:41Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-12-13T23:30:27Z</published>
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<id>urn:sha1:5360c683e6fe324376c11bfe5064ff1718f78c50</id>
<content type='text'>
Garrett Giordano &lt;ggiordano@phytec.com&gt; says:

This patch set adds the phyCORE AM62Ax board support and documenation to
u-boot.

The phyCORE-AM62Ax is a SoM (System on Module) featuring TI's AM62Ax SoC. It can
be used in combination with different carrier boards. This module can come
with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs
from the AM62x family.

A development Kit, called phyBOARD-Lyra is used as a carrier board reference
design around the AM62x SoM.

This series depends on the following two patches:
- [PATCH v2] arm: mach-k3: am62a7: Provide a way to obtain boot device for non SPL
  https://lists.denx.de/pipermail/u-boot/2024-October/570156.html
- [PATCH] board: phytec: common: Introduce CONFIG_PHYTEC_K3_DDR_PATCH
  https://lists.denx.de/pipermail/u-boot/2024-November/571543.html

Link: https://lore.kernel.org/r/20241118231606.3161665-1-ggiordano@phytec.com
[trini: Fix warning in board/phytec/common/k3/board.c when
        CONFIG_EFI_HAVE_CAPSULE_SUPPORT is not enabled]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Merge patch series "Enable EFI capsule updates for PHYTEC K3 SoMs"</title>
<updated>2024-12-13T20:15:43Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-12-13T20:15:43Z</published>
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<id>urn:sha1:7917841b000d5f4732183844b34c4636c206f60e</id>
<content type='text'>
Wadim Egorov &lt;w.egorov@phytec.de&gt; says:

This implements capsule updates for all our K3 SoMs for
eMMC, OSPI NOR and uSD cards.

We can use capsule updates to update the bootloader on all our
supported flash devices.

Link: https://lore.kernel.org/r/20241127121736.1525948-1-w.egorov@phytec.de
</content>
</entry>
<entry>
<title>board: phytec: k3: Add EFI capsule update support</title>
<updated>2024-12-13T20:15:31Z</updated>
<author>
<name>Wadim Egorov</name>
<email>w.egorov@phytec.de</email>
</author>
<published>2024-11-27T12:17:35Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f9fc0b7a2e2e12ff845ea9db129c6664edc3e972'/>
<id>urn:sha1:f9fc0b7a2e2e12ff845ea9db129c6664edc3e972</id>
<content type='text'>
Implement EFI capsule update functionality for PHYTEC K3-based SoMs.
These SoMs feature various flash device options, including eMMC,
OSPI NOR, and uSD card at the board level.

This update provides the necessary logic to enable EFI capsule updates
across all three flash devices, ensuring flexible and robust firmware
upgrade capabilities.

The GUID is dynamically generated for the board, to get it:

  efidebug capsule esrt
  ========================================
  ESRT: fw_resource_count=3
  ESRT: fw_resource_count_max=3
  ESRT: fw_resource_version=1
  [entry 0]==============================
  ESRT: fw_class=C7D64D6D-10B2-54BC-A3BF-06A9DC3653D9
  ESRT: fw_type=unknown
  ESRT: fw_version=0
  ESRT: lowest_supported_fw_version=0
  ESRT: capsule_flags=0
  ESRT: last_attempt_version=0
  ESRT: last_attempt_status=success
  [entry 1]==============================
  ESRT: fw_class=09841C3F-F177-5D57-B1F6-754D92879205
  ESRT: fw_type=unknown
  ESRT: fw_version=0
  ESRT: lowest_supported_fw_version=0
  ESRT: capsule_flags=0
  ESRT: last_attempt_version=0
  ESRT: last_attempt_status=success
  [entry 2]==============================
  ESRT: fw_class=D11A9016-515E-503A-8872-3FF65384D0C4
  ESRT: fw_type=unknown
  ESRT: fw_version=0
  ESRT: lowest_supported_fw_version=0
  ESRT: capsule_flags=0
  ESRT: last_attempt_version=0
  ESRT: last_attempt_status=success
  ========================================

On the board (from uSD card containing capsule binaries at boot):

  load mmc 1:1 $loadaddr tiboot3-capsule.bin
  efidebug capsule update $loadaddr

  load mmc 1:1 $loadaddr tispl-capsule.bin
  efidebug capsule update $loadaddr

  load mmc 1:1 $loadaddr uboot-capsule.bin
  efidebug capsule update $loadaddr

The binaries will be flashed to the flash device you are booted from.

Signed-off-by: Wadim Egorov &lt;w.egorov@phytec.de&gt;
</content>
</entry>
<entry>
<title>board: phytec: common: Introduce CONFIG_PHYTEC_K3_DDR_PATCH</title>
<updated>2024-12-04T20:04:08Z</updated>
<author>
<name>Garrett Giordano</name>
<email>ggiordano@phytec.com</email>
</author>
<published>2024-11-12T20:40:23Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=893ae07cc9b0050d635aad704c1bdae41477734a'/>
<id>urn:sha1:893ae07cc9b0050d635aad704c1bdae41477734a</id>
<content type='text'>
Introduce CONFIG_PHYTEC_K3_DDR_PATCH to make DDR timing patch code
optional for PHYTEC K3 boards. This allows better control over which
boards receive DDR timing patches, rather than compiling the code for
all boards with K3_DDRSS enabled.

Also enable the feature by default for PHYCORE_AM62X_R5.

Signed-off-by: Garrett Giordano &lt;ggiordano@phytec.com&gt;
Reviewed-by: Wadim Egorov &lt;w.egorov@phytec.de&gt;
</content>
</entry>
<entry>
<title>board: phytec: imx93: Add eeprom-based hardware introspection</title>
<updated>2024-11-26T02:08:02Z</updated>
<author>
<name>Christoph Stoidner</name>
<email>c.stoidner@phytec.de</email>
</author>
<published>2024-11-20T16:31:42Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d3b9b799688968d947200b75ea964144ddf1b984'/>
<id>urn:sha1:d3b9b799688968d947200b75ea964144ddf1b984</id>
<content type='text'>
The phyCORE-i.MX 93 is available in various variants. Relevant variant
options for the spl/u-boot are:
- with or without HS400 support for the eMMC
- with 1GB ram chip, or 2GB ram chip

The phyCORE's eeprom contains all information about the existing variant
options. Add evaluation of the eeprom data to the spl/u-boot to
enable/disable HS400 and to select the appropriate ram configuration at
startup.

Signed-off-by: Christoph Stoidner &lt;c.stoidner@phytec.de&gt;
Reviewed-by: Wadim Egorov &lt;w.egorov@phytec.de&gt;
Reviewed-by: Yannic Moog &lt;y.moog@phytec.de&gt;
Tested-by: Primoz Fiser &lt;primoz.fiser@norik.com&gt;
</content>
</entry>
<entry>
<title>board: phytec: common: k3: Apply SoM-specific overlays to OS device tree</title>
<updated>2024-11-14T16:46:22Z</updated>
<author>
<name>Wadim Egorov</name>
<email>w.egorov@phytec.de</email>
</author>
<published>2024-10-30T16:48:15Z</published>
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<id>urn:sha1:a6870706640aa4e775a4f05f3c85e47e0d3e4b85</id>
<content type='text'>
Our SoMs are available in multiple configurations, managed via device
tree overlays. To determine the specific variant in use, we read the
EEPROM and apply the appropriate overlays during boot to the device tree
used by the OS.

Signed-off-by: Wadim Egorov &lt;w.egorov@phytec.de&gt;
Acked-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</content>
</entry>
<entry>
<title>board: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD</title>
<updated>2024-10-11T17:44:48Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-09-30T01:49:47Z</published>
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<id>urn:sha1:dac3ce976a9b06be5aadbd857c4b64a8c521c6d4</id>
<content type='text'>
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
</feed>
