u-boot.git/board/phytec/phycore_am62x, branch next

Kconfig: board: restyle

2026-06-25T20:06:55Z

Restyle all Kconfigs: Menu entries : no space left Menu attributes: 1 TAB Help text : 1 TAB + 2 spaces Signed-off-by: Johan Jonker Reviewed-by: Tom Rini

treewide: move bi_dram[] from bd to gd

2026-06-25T00:13:24Z

Currently, the bi_dram[] information is stored in the board info structure (bd). Because bd is only valid after reserve_board(), dram_init_banksize() must be called late in the initialization process. This limitation is problematic, as it forces us to rely on a variety of bespoke functions to determine board RAM, bank memory sizes, and other early setup requirements. By moving bi_dram[] into the global data (gd), we can run it earlier. This is particularly convenient since boards define their own dram_init_banksize() routines, which do not always rely on parsing Device Tree (DT) memory nodes. Additionally, U-Boot defaults to relocating to the top of the first memory bank. While boards currently use custom functions to override this behavior, having the DRAM bank information available earlier in gd makes relocating to a different bank trivial and standardizes the process. Reviewed-by: Anshul Dalal Tested-by: Michal Simek # Versal Gen 2 Vek385 Tested-by: Anshul Dalal Reviewed-by: Simon Glass Signed-off-by: Ilias Apalodimas Tested-by: Christophe Leroy (CS GROUP)

board: phytec: phycore_am62x: Add tifs-rm-cfg

2026-05-29T20:22:38Z

Add a separate tifs-rm-cfg.yaml so the TIFS bundle uses the trimmed TIFS view instead of reusing rm-cfg.yaml, matching the rest of the AM62 boards. Mirrors commit 964bda9e805d ("board: ti: am62x: tifs-rm-cfg: Add the missing tifs-rm-cfg:") for the phyCORE-AM62x SoM. Signed-off-by: Wadim Egorov

Merge patch series "board: k3: Sync rm-cfg with TIFS v11.02.09 firmware"

2026-03-13T20:58:17Z

Sparsh Kumar says: This series updates the Resource Management (RM) configuration files for AM62 family devices to align with the TIFS v11.02.09 firmware. Background ---------- With the latest TIFS firmware (v11.02.09), an additional virtual interrupt and event is reserved for MCU cores to DM usage on am62x, am62ax, and am62px devices. This series brings the rm-cfg and tifs-rm-cfg files in sync with these firmware changes across both TI reference boards and vendor boards. These changes are backward compatible with older TIFS firmware versions. Additionally, the am62x platform was originally introduced without a tifs-rm-cfg.yaml file, unlike other platforms in the AM62 family. This series addresses that gap and enables tifs-rm-cfg in binman for am625-sk and am62p-sk platforms. Changes ------- TI reference boards (patches 1-4): - Update rm-cfg.yaml for am62x, am62ax, am62px - Sync am62px tifs-rm-cfg.yaml with TIFS firmware template - Add missing tifs-rm-cfg.yaml for am62x - Enable tifs-rm-cfg in binman for am625-sk and am62p-sk Vendor boards (patches 5-9): - beagleplay (am62x-based) - phytec phycore_am62x - toradex verdin-am62 - phytec phycore_am62ax - toradex verdin-am62p with the required interrupt reservation. The tifs-rm-cfg.yaml files cannot be updated without access to the corresponding SysConfig files, as both rm-cfg.yaml and tifs-rm-cfg.yaml must remain in sync. Link: https://lore.kernel.org/r/20260225132425.3096103-1-sparsh-kumar@ti.com

board: phytec: rm-cfg: Update rm-cfg to reflect new resource reservation

2026-03-13T20:57:21Z

With the latest v11.02.09 TIFS firmware, an additional virtual interrupt and event is reserved for MCU cores to DM usage on am62x devices. Update the rm-cfg to reflect this new reservation. Signed-off-by: Sparsh Kumar

board: Correct usage of fdtfile=CONFIG_DEFAULT_FDT_FILE

2026-02-23T21:30:34Z

As explained in commit 03d2d5fc003f ("board: sifive: unmatched: set fdtfile with unquoted variable.") using the syntax of 'fdtfile=CONFIG_DEFAULT_FDT_FILE' in the plain text environment files will lead to extraneous and problematic "s in the output. This is fixed by using fdtfile=DEFAULT_FDT_FILE which was introduced recently. Acked-by: Peng Fan Signed-off-by: Tom Rini

board: phytec: Add PHYTEC mailing list to MAINTAINERS entries

2026-01-21T18:05:15Z

PHYTEC maintains an actively monitored mailing list for upstream activities: upstream@lists.phytec.de. Add it to the MAINTAINERS entries for PHYTEC boards we actively develop and contribute to. Signed-off-by: Wadim Egorov Acked-by: Teresa Remmet

spl: split spl_board_fixups to arch/board specific

2025-10-22T18:05:52Z

The current spl_board_fixups API allows for modification of spl_image before the SPL jumps to it. This can be used to modify the DT for the next boot stage, however the current API only allows either the machine arch or the board to use it. This limits the utility of the API as there might be certain fixups that should be applied to all boards sharing the same machine architecture with others being board specific. For TI's K3 specifically, this prevents us from performing architecture level fixups since a lot of TI boards are already making use of the spl_board_fixups API. Therefore this patch splits the API into two to allow both board and the architecture specific fixups. The order is kept as arch then board to give board specific fixups the precedence. Reviewed-by: Dhruva Gole Signed-off-by: Anshul Dalal Tested-by: Wadim Egorov

Merge tag 'u-boot-socfpga-next-20250930' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next

2025-09-30T22:11:23Z

SoCFPGA updates for v2025.10: CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762 This pull request brings a set of updates across SoCFPGA platforms covering Agilex5, Agilex7, N5X, and Stratix10. The changes include: * Agilex5 enhancements: - USB3.1 enablement and DWC3 host driver support - System Manager register configuration for USB3 - Watchdog timeout increase and SDMMC clock API integration - dcache handling improvements in SMC mailbox path - Enable SPL_SYS_DCACHE_OFF in defconfig * Clock driver improvements: - Introduce dt-bindings header for Agilex clocks - Add enable/disable API and EMAC clock selection fixes - Replace manual shifts with FIELD_GET usage * DDR updates: - IOSSM mailbox compatibility check - Correct DDR calibration status handling * Device tree changes: - Agilex5: disable cache allocation for reads - Stratix10: add NAND IP node - Enable driver model watchdog - Enable USB3.1 node for Agilex5 * Config cleanups: - Simplify Agilex7 VAB defconfig - Remove obsolete SYS_BOOTM_LEN from N5X VAB config - Enable CRC32 support for SoCFPGA - Increase USB hub debounce timeout Overall this set improves reliability of DDR and cache flows, adds missing USB and MMC features for Agilex5, and refines clock and configuration handling across platforms. This patch set has been tested on Agilex 5 devkit, and Agilex devkit.

board: phytec: phycore_am6xx: Update scriptaddr

2025-09-24T13:50:13Z

After switching our boards to standard boot, we observed that the kernel hangs when booting with the "script" boot method over the network. The original scriptaddr value was copied from ti_common.env and remained unused for some time. On phycore-am62x and phycore-am62ax, however, this address conflicts with the current location where ATF is loaded (CONFIG_K3_ATF_LOAD_ADDR). Move scriptaddr to 0x89100000, directly after fdtoverlay_addr_r. The phycore-am64x is not affected by this issue, but we update it as well to keep all phycore-am6xx boards consistent. Signed-off-by: Wadim Egorov Reviewed-by: Anshul Dalal