u-boot.git/board/phytec, branch v2024.01

tree-wide: Replace http:// link with https:// link for ti.com

2023-11-10T16:01:50Z

Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon

board: phytec: phycore_imx8mp: Add 4000MTS RAM timings based on PCB rev

2023-10-16T09:29:58Z

Starting with PCB revision 3 we can safely make use of higher RAM frequency again. Make use of the EEPROM detection to determine the revision and use the updated RAM timings for new SoMs. Signed-off-by: Teresa Remmet Reviewed-by: Yannic Moog Tested-by: Yannic Moog

board: phytec: phycore-imx8mp: Add EEPROM detection initialisation

2023-10-16T09:29:23Z

Add EEPROM detection initialisation for phyCORE-i.MX8MM and print SoM information during boot when successful. Signed-off-by: Teresa Remmet Reviewed-by: Yannic Moog Tested-by: Yannic Moog

board: phytec: common: phytec_som_detection: Add helper for PCB revision

2023-10-16T09:27:58Z

Add helper function to read out the PCB revision of a PHYTEC SoM. Signed-off-by: Teresa Remmet Reviewed-by: Yannic Moog Tested-by: Yannic Moog

board: phytec: phycore_imx8mp: Update 2GB RAM Timings

2023-10-16T09:27:58Z

Due to PCB layout constraints in PCB revisions until including 1549.2, a RAM frequency of 2 GHz can cause rare instabilities. Set the RAM frequency to 1.5 GHz to achieve a stable system under all conditions. Signed-off-by: Teresa Remmet Reviewed-by: Yannic Moog Tested-by: Yannic Moog

board: phytec: common: Add imx8m specific EEPROM detection support

2023-10-16T09:27:58Z

Add imx8m specific detection part. Which includes checking the EEPROM data for article number options. Signed-off-by: Teresa Remmet Reviewed-by: Yannic Moog Tested-by: Yannic Moog

board: phytec: Add common PHYTEC SoM detection

2023-10-16T09:27:58Z

Recent shipped PHYTEC SoMs come with an i2c EEPROM containing information about the hardware such as board revision and variant. This can be used for RAM detection and loading device tree overlays during kernel start. Signed-off-by: Teresa Remmet Reviewed-by: Yannic Moog Tested-by: Yannic Moog Reviewed-by: Fabio Estevam

treewide: rework linker symbol declarations in sections header

2023-08-09T13:21:42Z

1. Convert all linker symbols to char[] type so that we can get the corresponding address by calling array name 'var' or its address '&var'. In this way, we can avoid some potential issues[1]. 2. Remove unused symbol '_TEXT_BASE'. It has been abandoned and has not been referenced by any source code. 3. Move '__data_end' to the arch x86's own sections header as it's only used by x86 arch. 4. Remove some duplicate declared linker symbols. Now we use the standard header file to declare them. [1] This patch fixes the boot failure on MIPS target. Error log: SPL: Image overlaps SPL Fixes: 1b8a1be1a1f1 ("spl: spl_legacy: Fix spl_end address") Signed-off-by: Shiji Yang Reviewed-by: Tom Rini

board: phytec: phycore_imx8mm: Update lpddr4_timing

2023-07-13T09:29:40Z

Update RAM Timings for 2GB RAM based on DDR Controller Configuration Spreadsheet revision 22. Including the update of the refresh rate to workaround errata ERR050805. Signed-off-by: Cem Tenruh

global: Use proper project name U-Boot

2023-06-12T11:24:31Z

Use proper project name in comments, Kconfig, readmes. Reviewed-by: Neil Armstrong Acked-by: Ilias Apalodimas Reviewed-by: Stefan Roese Reviewed-by: Qu Wenruo Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com