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<title>u-boot.git/board/samtec, branch v2017.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>mx6sx: Add initial support for Samtec VIN|ING 2000 board</title>
<updated>2016-11-30T08:54:42+00:00</updated>
<author>
<name>Christoph Fritz</name>
<email>chf.fritz@googlemail.com</email>
</author>
<published>2016-11-29T15:13:40+00:00</published>
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<id>730d25443aa894a32b9f66ebde3bfbf64b73ac7a</id>
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This patch adds initial support for Samtec VIN|ING 2000 board.

Signed-off-by: Christoph Fritz &lt;chf.fritz@googlemail.com&gt;
Reviewed-by: Stefano Babic &lt;sbabic@denx.de&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
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<pre>
This patch adds initial support for Samtec VIN|ING 2000 board.

Signed-off-by: Christoph Fritz &lt;chf.fritz@googlemail.com&gt;
Reviewed-by: Stefano Babic &lt;sbabic@denx.de&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
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</entry>
<entry>
<title>arm: socfpga: vining_fpga: Adding handoff for SDRAM ctrlcfg.extratime1</title>
<updated>2016-10-27T06:03:10+00:00</updated>
<author>
<name>Chin Liang See</name>
<email>clsee@altera.com</email>
</author>
<published>2016-09-21T02:26:01+00:00</published>
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<id>1c140fd2b4e024dc50415c40e93d66c02c47ac1e</id>
<content type='text'>
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
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<pre>
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>arm: socfpga: Add samtec VIN|ING board</title>
<updated>2016-06-01T20:44:14+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2015-12-01T17:09:52+00:00</published>
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<id>569a191a864cee66e3d0763179e8688499de0377</id>
<content type='text'>
Add support for board based on the popular Altera Cyclone V SoC.
This board has the following properties:
 - 1 GiB of DRAM
 - 1 Gigabit ethernet
 - 1 USB gadget port
 - 1 USB host port with an on-board hub
 - 2 QSPI NORs connected to the Cadence QSPI core
 - Multiple I2C EEPROMs and one I2C temperature sensor

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
---
V2: Update the defconfig as per Tom's request
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<pre>
Add support for board based on the popular Altera Cyclone V SoC.
This board has the following properties:
 - 1 GiB of DRAM
 - 1 Gigabit ethernet
 - 1 USB gadget port
 - 1 USB host port with an on-board hub
 - 2 QSPI NORs connected to the Cadence QSPI core
 - Multiple I2C EEPROMs and one I2C temperature sensor

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
---
V2: Update the defconfig as per Tom's request
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