u-boot.git/board/sbc8548, branch v2009.01 Unnamed repository; edit this file 'description' to name the repository. mpc8xxx: LCRR[CLKDIV] is sometimes five bits 2008-12-20T00:20:25+00:00 Trent Piepho tpiepho@freescale.com 2008-12-03T23:16:34+00:00 a5d212a263c58cc746481bf1fc878510533ce7d6 On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com> 
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.

In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems.  It
should be safe as the fifth bit was defined as reserved and set to 0.

Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
85xx: Add PORDEVSR_PCI1 define 2008-12-04T09:15:43+00:00 Peter Tyser ptyser@xes-inc.com 2008-12-01T19:47:12+00:00 9427ccde0355a2ebf47454e8e1be59f5b9864e08 Add define used to determine if PCI1 interface is in PCI or PCIX mode. Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Andy Fleming <afleming@freescale.com> 
Add define used to determine if PCI1 interface is in PCI or PCIX mode.

Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
85xx: Add CPU 2 errata workaround to all 8548 boards 2008-12-04T04:46:42+00:00 Peter Tyser ptyser@xes-inc.com 2008-11-11T16:17:10+00:00 a2cd50ed6ef0ac6b127b3d6db756979a8336718d All mpc8548-based boards should implement the suggested workaround to CPU 2 errata. Without the workaround, its possible for the 8548's core to hang while executing a msync or mbar 0 instruction and a snoopable transaction from an I/O master tagged to make quick forward progress is present. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Andy Fleming <afleming@freescale.com> 
All mpc8548-based boards should implement the suggested workaround
to CPU 2 errata. Without the workaround, its possible for the
8548's core to hang while executing a msync or mbar 0 instruction
and a snoopable transaction from an I/O master tagged to make
quick forward progress is present.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>
85xx: remove the unused ddr_enable_ecc in the board file 2008-12-04T04:44:48+00:00 Dave Liu daveliu@freescale.com 2008-10-28T09:53:38+00:00 9b0ad1b1c7a15ff674978705c7c52264978dc5d8 The DDR controller of 8548/8544/8568/8572/8536 processors have the ECC data init feature, and the new DDR code is using the feature, and we don't need the way with DMA to init memory any more. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> 
The DDR controller of 8548/8544/8568/8572/8536 processors
have the ECC data init feature, and the new DDR code is
using the feature, and we don't need the way with DMA to
init memory any more.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Align end of bss by 4 bytes 2008-11-18T22:13:16+00:00 Selvamuthukumar selva.muthukumar@e-coninfotech.com 2008-10-16T17:24:03+00:00 9b827cf1720acda2473afa516956eab6f7cca9a1 Most of the bss initialization loop increments 4 bytes at a time. And the loop end is checked for an 'equal' condition. Make the bss end address aligned by 4, so that the loop will end as expected. Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> Signed-off-by: Wolfgang Denk <wd@denx.de> 
Most of the bss initialization loop increments 4 bytes
at a time. And the loop end is checked for an 'equal'
condition. Make the bss end address aligned by 4, so
that the loop will end as expected.

Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Coding Style cleanup, update CHANGELOG 2008-11-02T15:14:22+00:00 Wolfgang Denk wd@denx.de 2008-11-02T15:14:22+00:00 3cbd823116ea8b7c654e275a8c2fca87cd1f5dc5 Signed-off-by: Wolfgang Denk <wd@denx.de> 
Signed-off-by: Wolfgang Denk <wd@denx.de>
85xx: Convert all fsl_pci_init users to new APIs 2008-10-24T22:35:12+00:00 Kumar Gala galak@kernel.crashing.org 2008-10-21T13:28:33+00:00 2dba0dea98c0dee1799ffd6fd6eb541645dbbd98 Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS, MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup(). With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> 
Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS,
MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows()
and ft_fsl_pci_setup().

With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
Pass dimm parameters to populate populate controller options 2008-10-18T19:54:04+00:00 Haiying Wang Haiying.Wang@freescale.com 2008-10-03T16:36:55+00:00 dfb49108e4f86c2224e1f30124328b0de66ef72e Because some dimm parameters like n_ranks needs to be used with the board frequency to choose the board parameters like clk_adjust etc. in the board_specific_paramesters table of the board ddr file, we need to pass the dimm parameters to the board file. * move ddr dimm parameters header file from /cpu to /include directory. * add ddr dimm parameters to populate board specific options. * Fix fsl_ddr_board_options() for all the 8xxx boards which call this function. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> 
Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.

* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
rename CFG_ macros to CONFIG_SYS 2008-10-18T19:54:03+00:00 Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com 2008-10-16T13:01:15+00:00 6d0f6bcf337c5261c08fabe12982178c2c489d76 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
FSL DDR: Convert sbc8548 to new DDR code. 2008-08-27T16:43:51+00:00 Kumar Gala galak@kernel.crashing.org 2008-08-27T04:15:28+00:00 33b9079ba20926f14238fff863b68a98e938948e Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>