u-boot.git/board/sbc8548, branch v2014.01

Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx

2013-11-25T19:43:46Z

Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun

Driver/DDR: Moving Freescale DDR driver to a common driver

2013-11-25T19:43:43Z

Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun

board: powerpc: convert makefiles to Kbuild style

2013-11-01T15:42:12Z

Signed-off-by: Masahiro Yamada Cc: Wolfgang Denk Cc: Kim Phillips Cc: York Sun Cc: Stefan Roese

Coding Style cleanup: remove trailing white space

2013-10-14T20:06:53Z

Signed-off-by: Wolfgang Denk

powerpc: Fix CamelCase checkpatch warnings

2013-08-20T16:57:51Z

85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions. because of this code checkpatch script generates "WARNING: Avoid CamelCase". Convert variables name to normal naming convention and modify board, driver files with updated the new structure. Signed-off-by: Prabhakar Kushwaha Acked-by: York Sun

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24T13:44:38Z

Signed-off-by: Wolfgang Denk [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini

8xxx: Change all 8*xx_DDR addresses to 8xxx

2012-11-27T23:45:17Z

There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming Tested-by: Andy Fleming Acked-by: Kim Phillips

doc: cleanup - move board READMEs into respective board directories

2012-07-29T13:42:02Z

Also drop a few files referring to no longer / not yet supported boards. Signed-off-by: Wolfgang Denk Cc: Prafulla Wadaskar Cc: Stefan Roese Cc: Kim Phillips Cc: Andy Fleming Cc: Jason Jin Cc: Stefano Babic Cc: Daniel Schwierzeck Acked-by: Stefano Babic Acked-by: Daniel Schwierzeck

sbc8548: Fix up local bus init to be frequency aware

2012-01-11T19:59:17Z

The code here was copied from the mpc8548cds support, and it wasn't using the CONFIG_SYS_LBC_LCRR define, and was just unconditionally setting the LCRR_EADC bit. Snooping with a hardware debugger also showed we had LCRR_DBYP set, since we were setting it based on a read of an uninitialized lcrr read via clkdiv. Borrow from the code in the tqm85xx.c support to add LBC frequency aware masking of these bits. This change will correct reliability issues associated with trying to use the 128MB of LBC 100MHz SDRAM on this board. Thanks to Keith Savage for assistance in diagnosing the root cause of this. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala

sbc8548: enable support for hardware SPD errata workaround

2012-01-11T19:59:14Z

Existing boards by default have an issue where the LBC SDRAM SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51. After the hardware modification listed in the README is made, then the DDR2 SPD EEPROM appears at 0x53. So this implements a board specific get_spd() by taking advantage of the existing weak linkage, that 1st tries reading at 0x53 and then if that fails, it falls back to the old 0x51. Since the old dependency issue of "SPD implies no LBC SDRAM" gets removed with the hardware errata fix, remove that restriction in the code, so both LBC SDRAM and SPD can be selected. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala