u-boot.git/board/solidrun/mx6cuboxi, branch v2016.01

MAINTAINERS/mailmap: Update my email address

2016-01-11T16:22:43Z

Update my email address to the NXP account. Signed-off-by: Fabio Estevam

mx6cuboxi: Remove obsolete comment

2016-01-10T09:50:53Z

We currently support various versions of Solidrun mx6 boards, so remove the obsolete comment. Reported-by: Jon Nettleton Signed-off-by: Fabio Estevam Reviewed-by: Stefano Babic

mx6cuboxi: Fix the reset delay for the AR8035 PHY

2016-01-10T09:50:24Z

Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is registered") Ethernet is no longer functional: Booting from net ... FEC Waiting for PHY auto negotiation to complete......... TIMEOUT ! BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 BOOTP broadcast 4 This commit does not have an issue in itself, but it revelead a problem with the Ethernet initialization. As per the AR8035 datasheet: "For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied." So do as suggested and keep the reset low for 10ms. Also add a 100us delay after deasserting the reset line to guarantee that the PHY ID can be read correctly and the Atheros PHY can be loaded as per Troy Kisky's suggestion. Signed-off-by: Fabio Estevam Tested-by: Tom Rini

mx6: remove SYS_SOC from board Kconfig

2015-09-13T08:37:29Z

Remove duplicated SYS_SOC Kconfig entry from board Kconfig, because we have this entry in arch/arm/cpu/armv7/mx6/Kconfig. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Heiko Schocher Cc: Christian Gmeiner Cc: Stefan Roese Cc: Troy Kisky Cc: Nikita Kiryanov Cc: "Eric Bénard" Cc: Fabio Estevam Cc: Tim Harvey Cc: Marek Vasut Cc: Markus Niebel Cc: Otavio Salvador Acked-by: Stefan Roese Acked-by: Marek Vasut Acked-by: Christian Gmeiner Acked-by: Markus Niebel Acked-by: Troy Kisky Acked-by: Igor Grinberg

imx: mx6: ddr init MMDC according to ddr_type

2015-09-02T13:34:12Z

To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper. The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg when ddr_type is for DDR3. Later we can use ddr_type to initialize MMDC for LPDDR2. Initialize ddr_type for different boards which enable SPL. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Tim Harvey Cc: Stefan Roese Cc: Fabio Estevam Reviewed-by: Stefan Roese

imx: clock support enet2 anatop clock support

2015-09-02T13:29:14Z

To i.MX6SX/UL, two ethernet interfaces are supported. Add ENET2 clock support: 1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed. To value 1, only i.MX6SX/UL can pass the check. 2. Modify board code who use this api to follow new api prototype. Signed-off-by: Peng Fan Cc: Heiko Schocher Cc: Fabio Estevam Cc: Stefan Roese Cc: Nikolaos Pasaloukos Cc: Stefano Babic Reviewed-by: Stefan Roese

mx6cuboxi: Fix boot of hummingboard dual-lite

2015-06-15T10:12:59Z

Hummingboard dual-lite is picking the incorrect calibration structure. Fix it so that it can boot. While at it, also fix p1_mpdgctrl1 register to match Solid-run's setting. Reported-by: Andrei Gherzan Signed-off-by: Fabio Estevam Tested-by: Andrei Gherzan

mx6cuboxi: Mention Cubox-i in the README

2015-05-15T17:21:23Z

Cubox-i boards are also supported, so update the README file. Signed-off-by: Fabio Estevam

mx6cuboxi: Pull down PAD_ENET_RXD0/RXD1

2015-05-15T17:20:47Z

Configure PAD_ENET_RXD0/RXD1 pads as pull down because these pads are directly connected to the Atheros 8035/8030 although they should be functional only in the RMII mode - 8030. Signed-off-by: Rabeeh Khoury Signed-off-by: Fabio Estevam Reviewed-by: Stefano Babic Reviewed-by: Tom Rini Tested-By: Vagrant Cascadian

mx6cuboxi: Fix Ethernet PHY detection problem

2015-05-15T17:20:47Z

mx6cuboxi sometimes fails to recognize the Ethernet PHY: Net: Phy 0 not found The explanation for this behavior comes from from Rabeeh Khoury: "The LED_ACT pin on the carrier-one boards had a pull down that forces the phy address to 0x0; where on CuBox-i and the production HummingBoard that pin is connected directly to LED that depending on the pull down strength of the LED it might be sampled as '0' or '1' thus the phy address might appear as either address 0x0 or 0x4." "This is AR8035 implementation; in reset stage the LED pin is configured as input, and pull up/down does matter. In this case it configures the PHY address. After reset is deasserted the same LED pin becomes output and then according to the previous pull/up it should be active high/low" One way to properly fix this behavior is to place external pull-up/down resistors in the LED line, but from a software standpoint we can fix it by telling phy_find_by_mask() to scan the PHY at addresses 0x0 and 0x4. Reported-by: Vagrant Cascadian Signed-off-by: Rabeeh Khoury Signed-off-by: Fabio Estevam Acked-by: Stefano Babic Reviewed-by: Tom Rini Tested-By: Vagrant Cascadian