u-boot.git/board/solidrun, branch master

board: solidrun: clearfog: enable ddr odt0 on write for both chip-select

2025-01-28T08:08:44+00:00

Enabling ODT is required to suppress reflection of the data signal on
DDR write operation. SolidRun Armada 388 SoM only connects M_ODT[0] even
when both chip-select are used.

Enable ODT[0] for both chip-select during write only.

Original work by Baruch Siach [1] and Chris Packham [2].

[1] https://github.com/SolidRun/u-boot-armada38x/commit/aba763a611e69fbcc4e229659da9d84f16b39814
[2] https://github.com/SolidRun/u-boot-armada38x/commit/dbaf09590df9add19e738d2de03c0f2d0d8f5433

Signed-off-by: Josua Mayer 
Reviewed-by: Stefan Roese

net: fec_mxc: fix probing for imx8qxp

2024-11-26T02:07:37+00:00

probing on capricorn board (imx8qxp based) brings:

Can't find FEC0 clk rate: -19

Cause is that when probing fec_mxc driver, fec_mii_setspeed()
is called which calls fec_get_clk_rate().

fec_mii_setspeed() calls fec_get_clk_rate with NULL pointer
for udev and so as in IMX8QXP case CLK_CCF is enabled
udev gets searched with:

uclass_get_device_by_seq(UCLASS_ETH, idx, &dev);

but we do not have yet a UCLASS_ETH ! as we just probing it!

Prevent this by passing udev to fec_get_clk_rate()

Signed-off-by: Heiko Schocher

board: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11T17:44:48+00:00

Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass

Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"

2024-05-20T19:35:03+00:00

As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman 
Signed-off-by: Tom Rini

Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""

2024-05-19T14:16:36+00:00

When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman 
Signed-off-by: Tom Rini

board: solidrun: Remove and add needed includes

2024-05-07T14:00:40+00:00

Remove  from this board vendor directory and when needed
add missing include files directly.

Signed-off-by: Tom Rini

mx6cuboxi: Do not print devicetree model

2024-04-05T12:37:56+00:00

The mx6cuboxi_defconfig target supports several board
variants. All of these variants use the hummingboard devicetree in U-Boot.

Currently, the devicetree model as well as the board variant name
are shown:

...
Model: SolidRun HummingBoard2 Dual/Quad (1.5som+emmc)
Board: MX6 Cubox-i
...

Printing the devicetree model that is used internally by U-Boot
may confuse users.

Unselect the CONFIG_DISPLAY_BOARDINFO option so that only the
board name is printed in board_late_init() instead.

Signed-off-by: Fabio Estevam 
Tested-by: Christian Gmeiner

mx6cuboxi: Fix board revision detection

2024-03-30T12:49:12+00:00

Currently, an i.MX6 Cuboxi board is incorrectly detected
as the HummingBoard model:

U-Boot 2024.04-rc5 (Mar 26 2024 - 15:59:22 +0100)

CPU:   Freescale i.MX6Q rev1.3 996 MHz (running at 792 MHz)
CPU:   Extended Commercial temperature grade (-20C to 105C) at 26C
Reset cause: POR
Model: SolidRun HummingBoard2 Dual/Quad (1.5som+emmc)
gpio@20a4000: set_dir_flags: error: gpio GPIO3_8 not reserved
gpio@20a4000: get_value: error: gpio GPIO3_8 not reserved
gpio@20a8000: set_dir_flags: error: gpio GPIO4_4 not reserved
gpio@20a8000: get_value: error: gpio GPIO4_4 not reserved
gpio@20b0000: set_dir_flags: error: gpio GPIO6_9 not reserved
gpio@20b0000: get_value: error: gpio GPIO6_9 not reserved
Board: MX6 HummingBoard
DRAM:  2 GiB
...

This error happens because request_detect_gpios() uses the GPIO DM
API, but board_type() still uses the legacy non-DM GPIO API.

Fix it by using the GPIO DM API in board_type() to read the
board revision pins in SPL.

Reported-by: Christian Gmeiner 
Signed-off-by: Fabio Estevam 
Tested-by: Christian Gmeiner

board: solidrun: clearfog: fix serdes 1 / eth2 speed for clearfog gtr

2024-01-22T11:47:45+00:00

Clearfog GTR connects eth2 / serdes 1 to a 2.5Gbps capable ethernet
switch port. Linux already configures a fixed-link at speed 2500 from
device-tree.

Upgrade serdes 1 rate to 3.125Gbps to support a 2.5Gbps link.

Additionally add comments documenting each serdes' function of clearfog
gtr, which are shared with clearfog pro.

Signed-off-by: Josua Mayer

arm: mvebu: clearfog gtr: add config option to select serdes0 interface

2024-01-22T11:47:45+00:00

Clearfog GTR has an assembly option for a SATA connector, CON18.
It shares the serdes with mini-pcie connector CON3.

Add new kconfig option to select betweenata and pci, defaulting to pci
as it was previously configured in board-file.

Clearfog GTR connects eth2 / serdes 1 to a 2.5Gbps capable ethernet
switch port. Linux already configures a fixed-link at speed 2500 from
device-tree.
Upgrade serdes 1 rate to 3.125Gbps to support a 2.5Gbps network link on
Clearfog GTR.

Signed-off-by: Josua Mayer