<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/board/solidrun, branch v2017.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>imx: imx6: Move gpr_init() function to soc.c</title>
<updated>2017-08-28T07:48:53+00:00</updated>
<author>
<name>Breno Lima</name>
<email>breno.lima@nxp.com</email>
</author>
<published>2017-08-24T13:00:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3aa4b703b483f165dd2eb5c3324b44b60fbb1672'/>
<id>3aa4b703b483f165dd2eb5c3324b44b60fbb1672</id>
<content type='text'>
Since the gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
MX6Q and MX6QP processors move it to the soc.c file.

Signed-off-by: Breno Lima &lt;breno.lima@nxp.com&gt;
Acked-by: Stefano Babic &lt;sbabic@denx.de&gt;
Reviewed-by: Lukasz Majewski &lt;lukma@denx.de&gt;
Reviewed-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Since the gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
MX6Q and MX6QP processors move it to the soc.c file.

Signed-off-by: Breno Lima &lt;breno.lima@nxp.com&gt;
Acked-by: Stefano Babic &lt;sbabic@denx.de&gt;
Reviewed-by: Lukasz Majewski &lt;lukma@denx.de&gt;
Reviewed-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>env: Rename setenv() to env_set()</title>
<updated>2017-08-16T12:22:18+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-08-03T18:22:09+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=382bee57f19b4454e2015bc19a010bc2d0ab9337'/>
<id>382bee57f19b4454e2015bc19a010bc2d0ab9337</id>
<content type='text'>
We are now using an env_ prefix for environment functions. Rename setenv()
for consistency. Also add function comments in common.h.

Suggested-by: Wolfgang Denk &lt;wd@denx.de&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
We are now using an env_ prefix for environment functions. Rename setenv()
for consistency. Also add function comments in common.h.

Suggested-by: Wolfgang Denk &lt;wd@denx.de&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://www.denx.de/git/u-boot-imx</title>
<updated>2017-07-18T12:42:48+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-07-18T12:42:48+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=39632b4a01210e329333d787d828157dcd2c7328'/>
<id>39632b4a01210e329333d787d828157dcd2c7328</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>imx: reorganize IMX code as other SOCs</title>
<updated>2017-07-12T08:17:44+00:00</updated>
<author>
<name>Stefano Babic</name>
<email>sbabic@denx.de</email>
</author>
<published>2017-06-29T08:16:06+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=552a848e4f75e224515269a84a1155c84b762bc7'/>
<id>552a848e4f75e224515269a84a1155c84b762bc7</id>
<content type='text'>
Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/&lt;SOC&gt;.

This change is also coherent with the structure in kernel.

Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;

CC: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
CC: Akshay Bhat &lt;akshaybhat@timesys.com&gt;
CC: Ken Lin &lt;Ken.Lin@advantech.com.tw&gt;
CC: Marek Vasut &lt;marek.vasut@gmail.com&gt;
CC: Heiko Schocher &lt;hs@denx.de&gt;
CC: "Sébastien Szymanski" &lt;sebastien.szymanski@armadeus.com&gt;
CC: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
CC: Stefan Roese &lt;sr@denx.de&gt;
CC: Patrick Bruenn &lt;p.bruenn@beckhoff.com&gt;
CC: Troy Kisky &lt;troy.kisky@boundarydevices.com&gt;
CC: Nikita Kiryanov &lt;nikita@compulab.co.il&gt;
CC: Otavio Salvador &lt;otavio@ossystems.com.br&gt;
CC: "Eric Bénard" &lt;eric@eukrea.com&gt;
CC: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
CC: Ye Li &lt;ye.li@nxp.com&gt;
CC: Peng Fan &lt;peng.fan@nxp.com&gt;
CC: Adrian Alonso &lt;adrian.alonso@nxp.com&gt;
CC: Alison Wang &lt;b18965@freescale.com&gt;
CC: Tim Harvey &lt;tharvey@gateworks.com&gt;
CC: Martin Donnelly &lt;martin.donnelly@ge.com&gt;
CC: Marcin Niestroj &lt;m.niestroj@grinn-global.com&gt;
CC: Lukasz Majewski &lt;lukma@denx.de&gt;
CC: Adam Ford &lt;aford173@gmail.com&gt;
CC: "Albert ARIBAUD (3ADEV)" &lt;albert.aribaud@3adev.fr&gt;
CC: Boris Brezillon &lt;boris.brezillon@free-electrons.com&gt;
CC: Soeren Moch &lt;smoch@web.de&gt;
CC: Richard Hu &lt;richard.hu@technexion.com&gt;
CC: Wig Cheng &lt;wig.cheng@technexion.com&gt;
CC: Vanessa Maegima &lt;vanessa.maegima@nxp.com&gt;
CC: Max Krummenacher &lt;max.krummenacher@toradex.com&gt;
CC: Stefan Agner &lt;stefan.agner@toradex.com&gt;
CC: Markus Niebel &lt;Markus.Niebel@tq-group.com&gt;
CC: Breno Lima &lt;breno.lima@nxp.com&gt;
CC: Francesco Montefoschi &lt;francesco.montefoschi@udoo.org&gt;
CC: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
CC: Scott Wood &lt;oss@buserror.net&gt;
CC: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
CC: Anatolij Gustschin &lt;agust@denx.de&gt;
CC: Simon Glass &lt;sjg@chromium.org&gt;
CC: "Andrew F. Davis" &lt;afd@ti.com&gt;
CC: "Łukasz Majewski" &lt;l.majewski@samsung.com&gt;
CC: Patrice Chotard &lt;patrice.chotard@st.com&gt;
CC: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
CC: Hans de Goede &lt;hdegoede@redhat.com&gt;
CC: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
CC: Stephen Warren &lt;swarren@nvidia.com&gt;
CC: Andre Przywara &lt;andre.przywara@arm.com&gt;
CC: "Álvaro Fernández Rojas" &lt;noltari@gmail.com&gt;
CC: York Sun &lt;york.sun@nxp.com&gt;
CC: Xiaoliang Yang &lt;xiaoliang.yang@nxp.com&gt;
CC: Chen-Yu Tsai &lt;wens@csie.org&gt;
CC: George McCollister &lt;george.mccollister@gmail.com&gt;
CC: Sven Ebenfeld &lt;sven.ebenfeld@gmail.com&gt;
CC: Filip Brozovic &lt;fbrozovic@gmail.com&gt;
CC: Petr Kulhavy &lt;brain@jikos.cz&gt;
CC: Eric Nelson &lt;eric@nelint.com&gt;
CC: Bai Ping &lt;ping.bai@nxp.com&gt;
CC: Anson Huang &lt;Anson.Huang@nxp.com&gt;
CC: Sanchayan Maity &lt;maitysanchayan@gmail.com&gt;
CC: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
CC: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
CC: Gary Bisson &lt;gary.bisson@boundarydevices.com&gt;
CC: Alexander Graf &lt;agraf@suse.de&gt;
CC: u-boot@lists.denx.de
Reviewed-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Reviewed-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/&lt;SOC&gt;.

This change is also coherent with the structure in kernel.

Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;

CC: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
CC: Akshay Bhat &lt;akshaybhat@timesys.com&gt;
CC: Ken Lin &lt;Ken.Lin@advantech.com.tw&gt;
CC: Marek Vasut &lt;marek.vasut@gmail.com&gt;
CC: Heiko Schocher &lt;hs@denx.de&gt;
CC: "Sébastien Szymanski" &lt;sebastien.szymanski@armadeus.com&gt;
CC: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
CC: Stefan Roese &lt;sr@denx.de&gt;
CC: Patrick Bruenn &lt;p.bruenn@beckhoff.com&gt;
CC: Troy Kisky &lt;troy.kisky@boundarydevices.com&gt;
CC: Nikita Kiryanov &lt;nikita@compulab.co.il&gt;
CC: Otavio Salvador &lt;otavio@ossystems.com.br&gt;
CC: "Eric Bénard" &lt;eric@eukrea.com&gt;
CC: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
CC: Ye Li &lt;ye.li@nxp.com&gt;
CC: Peng Fan &lt;peng.fan@nxp.com&gt;
CC: Adrian Alonso &lt;adrian.alonso@nxp.com&gt;
CC: Alison Wang &lt;b18965@freescale.com&gt;
CC: Tim Harvey &lt;tharvey@gateworks.com&gt;
CC: Martin Donnelly &lt;martin.donnelly@ge.com&gt;
CC: Marcin Niestroj &lt;m.niestroj@grinn-global.com&gt;
CC: Lukasz Majewski &lt;lukma@denx.de&gt;
CC: Adam Ford &lt;aford173@gmail.com&gt;
CC: "Albert ARIBAUD (3ADEV)" &lt;albert.aribaud@3adev.fr&gt;
CC: Boris Brezillon &lt;boris.brezillon@free-electrons.com&gt;
CC: Soeren Moch &lt;smoch@web.de&gt;
CC: Richard Hu &lt;richard.hu@technexion.com&gt;
CC: Wig Cheng &lt;wig.cheng@technexion.com&gt;
CC: Vanessa Maegima &lt;vanessa.maegima@nxp.com&gt;
CC: Max Krummenacher &lt;max.krummenacher@toradex.com&gt;
CC: Stefan Agner &lt;stefan.agner@toradex.com&gt;
CC: Markus Niebel &lt;Markus.Niebel@tq-group.com&gt;
CC: Breno Lima &lt;breno.lima@nxp.com&gt;
CC: Francesco Montefoschi &lt;francesco.montefoschi@udoo.org&gt;
CC: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
CC: Scott Wood &lt;oss@buserror.net&gt;
CC: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
CC: Anatolij Gustschin &lt;agust@denx.de&gt;
CC: Simon Glass &lt;sjg@chromium.org&gt;
CC: "Andrew F. Davis" &lt;afd@ti.com&gt;
CC: "Łukasz Majewski" &lt;l.majewski@samsung.com&gt;
CC: Patrice Chotard &lt;patrice.chotard@st.com&gt;
CC: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
CC: Hans de Goede &lt;hdegoede@redhat.com&gt;
CC: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
CC: Stephen Warren &lt;swarren@nvidia.com&gt;
CC: Andre Przywara &lt;andre.przywara@arm.com&gt;
CC: "Álvaro Fernández Rojas" &lt;noltari@gmail.com&gt;
CC: York Sun &lt;york.sun@nxp.com&gt;
CC: Xiaoliang Yang &lt;xiaoliang.yang@nxp.com&gt;
CC: Chen-Yu Tsai &lt;wens@csie.org&gt;
CC: George McCollister &lt;george.mccollister@gmail.com&gt;
CC: Sven Ebenfeld &lt;sven.ebenfeld@gmail.com&gt;
CC: Filip Brozovic &lt;fbrozovic@gmail.com&gt;
CC: Petr Kulhavy &lt;brain@jikos.cz&gt;
CC: Eric Nelson &lt;eric@nelint.com&gt;
CC: Bai Ping &lt;ping.bai@nxp.com&gt;
CC: Anson Huang &lt;Anson.Huang@nxp.com&gt;
CC: Sanchayan Maity &lt;maitysanchayan@gmail.com&gt;
CC: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
CC: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
CC: Gary Bisson &lt;gary.bisson@boundarydevices.com&gt;
CC: Alexander Graf &lt;agraf@suse.de&gt;
CC: u-boot@lists.denx.de
Reviewed-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Reviewed-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mx6cuboxi: Add support for sata</title>
<updated>2017-07-12T07:44:22+00:00</updated>
<author>
<name>Peter Robinson</name>
<email>pbrobinson@gmail.com</email>
</author>
<published>2017-07-01T17:44:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ff1815632563a826cfe49fc9496a36d00febb6e3'/>
<id>ff1815632563a826cfe49fc9496a36d00febb6e3</id>
<content type='text'>
The Cubox-i and Hummingboard series of devices have an option of
SATA on board, and depending on how the fuses are blown even the
option to boot SPL from SATA. So enable support for it so it can
be used to boot the OS from if people desire.

Cc: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Signed-off-by: Peter Robinson &lt;pbrobinson@gmail.com&gt;
Acked-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The Cubox-i and Hummingboard series of devices have an option of
SATA on board, and depending on how the fuses are blown even the
option to boot SPL from SATA. So enable support for it so it can
be used to boot the OS from if people desire.

Cc: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Signed-off-by: Peter Robinson &lt;pbrobinson@gmail.com&gt;
Acked-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: mvebu: clearfog: fix chip name comment</title>
<updated>2017-07-12T04:57:55+00:00</updated>
<author>
<name>Baruch Siach</name>
<email>baruch@tkos.co.il</email>
</author>
<published>2017-07-04T17:23:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=172b2e0b561a50a3d8c4275be4ed24b0c8e18896'/>
<id>172b2e0b561a50a3d8c4275be4ed24b0c8e18896</id>
<content type='text'>
The clearfog uses Armada 388.

Cc: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Baruch Siach &lt;baruch@tkos.co.il&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The clearfog uses Armada 388.

Cc: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Baruch Siach &lt;baruch@tkos.co.il&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>driver/ddr: Add support for setting timing in hws_topology_map</title>
<updated>2017-07-12T04:56:48+00:00</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2017-06-09T17:28:40+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=90bcc3d38d2b1159e1b80da050f6163e5c3f575d'/>
<id>90bcc3d38d2b1159e1b80da050f6163e5c3f575d</id>
<content type='text'>
The DDR3 training code for Marvell A38X currently computes 1t timing
when given board topology map of the Turris Omnia, but Omnia needs 2t.

This patch adds support for enforcing the 2t timing in struct
hws_topology_map, through a new enum hws_timing, which can assume
following values:
  HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t
                    from the number of CSs
  HWS_TIM_1T      - enforce 1t
  HWS_TIM_2T      - enforce 2t

This patch also sets all the board topology maps (db-88f6820-amc,
db-88f6820-gp, controlcenterdc and clearfog) to have timing set to
HWS_TIM_DEFAULT.

Signed-off-by: Marek Behun &lt;marek.behun@nic.cz&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The DDR3 training code for Marvell A38X currently computes 1t timing
when given board topology map of the Turris Omnia, but Omnia needs 2t.

This patch adds support for enforcing the 2t timing in struct
hws_topology_map, through a new enum hws_timing, which can assume
following values:
  HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t
                    from the number of CSs
  HWS_TIM_1T      - enforce 1t
  HWS_TIM_2T      - enforce 2t

This patch also sets all the board topology maps (db-88f6820-amc,
db-88f6820-gp, controlcenterdc and clearfog) to have timing set to
HWS_TIM_DEFAULT.

Signed-off-by: Marek Behun &lt;marek.behun@nic.cz&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: mvebu: clearfog: reset uSOM onboard 1512 phy</title>
<updated>2017-05-31T05:42:40+00:00</updated>
<author>
<name>Patrick Wildt</name>
<email>patrick@blueri.se</email>
</author>
<published>2017-05-09T11:54:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fb9765d5f9a1fbe7ca9c472cca9ceb561b02c1a1'/>
<id>fb9765d5f9a1fbe7ca9c472cca9ceb561b02c1a1</id>
<content type='text'>
Use GPIO19 which is wired to the uSOM phy reset signal in order to reset
the uSOM's 1512 Gigabit Ethernet phy.

This GPIO is valid on ClearFog rev 2.1 and newer.

Taken from SolidRun's specialised u-boot, see
https://github.com/SolidRun/u-boot-armada38x/commit/f906e3df172e07ac82cdd87b278d7896949262ea

Signed-off-by: Patrick Wildt &lt;patrick@blueri.se&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Use GPIO19 which is wired to the uSOM phy reset signal in order to reset
the uSOM's 1512 Gigabit Ethernet phy.

This GPIO is valid on ClearFog rev 2.1 and newer.

Taken from SolidRun's specialised u-boot, see
https://github.com/SolidRun/u-boot-armada38x/commit/f906e3df172e07ac82cdd87b278d7896949262ea

Signed-off-by: Patrick Wildt &lt;patrick@blueri.se&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>treewide: replace #include &lt;asm/errno.h&gt; with &lt;linux/errno.h&gt;</title>
<updated>2016-09-23T21:55:42+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2016-09-21T02:28:55+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1221ce459d04a428f8880f58581f671b736c3c27'/>
<id>1221ce459d04a428f8880f58581f671b736c3c27</id>
<content type='text'>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap &lt;asm-generic/errno.h&gt;)

Replace all include directives for &lt;asm/errno.h&gt; with &lt;linux/errno.h&gt;.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap &lt;asm-generic/errno.h&gt;)

Replace all include directives for &lt;asm/errno.h&gt; with &lt;linux/errno.h&gt;.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mx6: ddr: Allow changing REFSEL and REFR fields</title>
<updated>2016-09-06T16:22:48+00:00</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2016-08-29T23:37:15+00:00</published>
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Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.

Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:

$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4      0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800

So introduce a mechanism for users to be able to configure
REFSEL and REFR fields as needed.

Keep all the mx6 SPL users in their current REF_SEL and REFR values,
so no functional changes for the existing users.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Reviewed-by: Eric Nelson &lt;eric@nelint.com&gt;
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<pre>
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.

Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:

$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4      0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800

So introduce a mechanism for users to be able to configure
REFSEL and REFR fields as needed.

Keep all the mx6 SPL users in their current REF_SEL and REFR values,
so no functional changes for the existing users.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Reviewed-by: Eric Nelson &lt;eric@nelint.com&gt;
</pre>
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