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<title>u-boot.git/board/solidrun, branch v2024.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board/solidrun?h=v2024.04</id>
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<updated>2024-03-30T12:49:12Z</updated>
<entry>
<title>mx6cuboxi: Fix board revision detection</title>
<updated>2024-03-30T12:49:12Z</updated>
<author>
<name>Fabio Estevam</name>
<email>festevam@gmail.com</email>
</author>
<published>2024-03-27T11:49:59Z</published>
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<id>urn:sha1:e7b5250612ed4ffbf962911d49c6bb4c520eb1f2</id>
<content type='text'>
Currently, an i.MX6 Cuboxi board is incorrectly detected
as the HummingBoard model:

U-Boot 2024.04-rc5 (Mar 26 2024 - 15:59:22 +0100)

CPU:   Freescale i.MX6Q rev1.3 996 MHz (running at 792 MHz)
CPU:   Extended Commercial temperature grade (-20C to 105C) at 26C
Reset cause: POR
Model: SolidRun HummingBoard2 Dual/Quad (1.5som+emmc)
gpio@20a4000: set_dir_flags: error: gpio GPIO3_8 not reserved
gpio@20a4000: get_value: error: gpio GPIO3_8 not reserved
gpio@20a8000: set_dir_flags: error: gpio GPIO4_4 not reserved
gpio@20a8000: get_value: error: gpio GPIO4_4 not reserved
gpio@20b0000: set_dir_flags: error: gpio GPIO6_9 not reserved
gpio@20b0000: get_value: error: gpio GPIO6_9 not reserved
Board: MX6 HummingBoard
DRAM:  2 GiB
...

This error happens because request_detect_gpios() uses the GPIO DM
API, but board_type() still uses the legacy non-DM GPIO API.

Fix it by using the GPIO DM API in board_type() to read the
board revision pins in SPL.

Reported-by: Christian Gmeiner &lt;cgmeiner@igalia.com&gt;
Signed-off-by: Fabio Estevam &lt;festevam@gmail.com&gt;
Tested-by: Christian Gmeiner &lt;cgmeiner@igalia.com&gt;
</content>
</entry>
<entry>
<title>board: solidrun: clearfog: fix serdes 1 / eth2 speed for clearfog gtr</title>
<updated>2024-01-22T11:47:45Z</updated>
<author>
<name>Josua Mayer</name>
<email>josua@solid-run.com</email>
</author>
<published>2024-01-12T13:35:11Z</published>
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<id>urn:sha1:bb6e89048ceaf26a4d775750715e3279dbd73d07</id>
<content type='text'>
Clearfog GTR connects eth2 / serdes 1 to a 2.5Gbps capable ethernet
switch port. Linux already configures a fixed-link at speed 2500 from
device-tree.

Upgrade serdes 1 rate to 3.125Gbps to support a 2.5Gbps link.

Additionally add comments documenting each serdes' function of clearfog
gtr, which are shared with clearfog pro.

Signed-off-by: Josua Mayer &lt;josua@solid-run.com&gt;
</content>
</entry>
<entry>
<title>arm: mvebu: clearfog gtr: add config option to select serdes0 interface</title>
<updated>2024-01-22T11:47:45Z</updated>
<author>
<name>Josua Mayer</name>
<email>josua@solid-run.com</email>
</author>
<published>2024-01-12T13:35:10Z</published>
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<id>urn:sha1:26c7de353f3d6fea1f2cc93764a6db1a9191b20f</id>
<content type='text'>
Clearfog GTR has an assembly option for a SATA connector, CON18.
It shares the serdes with mini-pcie connector CON3.

Add new kconfig option to select betweenata and pci, defaulting to pci
as it was previously configured in board-file.

Clearfog GTR connects eth2 / serdes 1 to a 2.5Gbps capable ethernet
switch port. Linux already configures a fixed-link at speed 2500 from
device-tree.
Upgrade serdes 1 rate to 3.125Gbps to support a 2.5Gbps network link on
Clearfog GTR.

Signed-off-by: Josua Mayer &lt;josua@solid-run.com&gt;
</content>
</entry>
<entry>
<title>solidrun: Use checkboard() instead of show_board_info()</title>
<updated>2023-11-28T17:53:03Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-11-13T02:58:24Z</published>
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<id>urn:sha1:56720b2ce2168dd708dfed344b2dcc3ad6ce7617</id>
<content type='text'>
Boards can use a sysinfo driver if a particular model name is needed.
Update this board to use checkboard() directly, rather than having a
weak function laid on top of a weak function.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>arm: mvebu: clearfog: support 512MB memory size from tlv eeprom</title>
<updated>2023-10-16T12:00:45Z</updated>
<author>
<name>Josua Mayer</name>
<email>josua@solid-run.com</email>
</author>
<published>2023-10-08T14:58:04Z</published>
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<id>urn:sha1:ebf1de9372fa84dbc5805776cbd7ea2add703255</id>
<content type='text'>
Handle 2GBit memory size value "2" from tlv eeprom on ddr
initialisation, to support SoMs with 512MB ddr memory.

Signed-off-by: Josua Mayer &lt;josua@solid-run.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: mvebu: clearfog: read number of ddr channels from tlv data</title>
<updated>2023-10-16T12:00:45Z</updated>
<author>
<name>Josua Mayer</name>
<email>josua@solid-run.com</email>
</author>
<published>2023-10-08T14:58:03Z</published>
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<id>urn:sha1:fdd6069515d68e743e6aeb7982ba81c9b7905ad2</id>
<content type='text'>
Extend the existing tlv vendor extension used for ram size by one byte to
also store the number of ddr channels.
The length of the tlv entry can indicate whether the new information is
present. If not default to single channel.

Signed-off-by: Josua Mayer &lt;josua@solid-run.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>treewide: rework linker symbol declarations in sections header</title>
<updated>2023-08-09T13:21:42Z</updated>
<author>
<name>Shiji Yang</name>
<email>yangshiji66@outlook.com</email>
</author>
<published>2023-08-03T01:47:16Z</published>
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<id>urn:sha1:506df9dc5881b74ca6463b89e9edcd14732a7da5</id>
<content type='text'>
1. Convert all linker symbols to char[] type so that we can get the
   corresponding address by calling array name 'var' or its address
   '&amp;var'. In this way, we can avoid some potential issues[1].
2. Remove unused symbol '_TEXT_BASE'. It has been abandoned and has
   not been referenced by any source code.
3. Move '__data_end' to the arch x86's own sections header as it's
   only used by x86 arch.
4. Remove some duplicate declared linker symbols. Now we use the
   standard header file to declare them.

[1] This patch fixes the boot failure on MIPS target. Error log:
SPL: Image overlaps SPL

Fixes: 1b8a1be1a1f1 ("spl: spl_legacy: Fix spl_end address")
Signed-off-by: Shiji Yang &lt;yangshiji66@outlook.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>MAINTAINERS: Fix path typos and similar</title>
<updated>2023-07-25T16:44:47Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-07-18T23:33:32Z</published>
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<id>urn:sha1:5f1720f282043b86d7755ef975d3a813733d3944</id>
<content type='text'>
We have a number of cases where the in-tree path of files and where
they presumably were when the first version of a patch were posted
differ slightly.  Correct these to point at where the files are now.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>MAINTAINERS: Add some missing defconfig files to existing entries</title>
<updated>2023-07-25T16:44:47Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-07-18T16:20:25Z</published>
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<id>urn:sha1:e5478bef263ff5255ee4a81a47b1fd58dc6cb44b</id>
<content type='text'>
We have a few places where defconfigs were added (or renamed) and not
included in their previously listed MAINTAINERS entry, correct this.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Acked-by:  Adam Ford &lt;aford173@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>solidrun: mx6cuboxi: use CONFIG_IS_ENABLED(SATA) instead of ifdef CONFIG_SATA</title>
<updated>2023-05-10T20:45:42Z</updated>
<author>
<name>Troy Kisky</name>
<email>troykiskyboundary@gmail.com</email>
</author>
<published>2023-03-13T21:31:40Z</published>
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<id>urn:sha1:ff286fbc5153d0a15465faf0a8f1cc6f80dc33a8</id>
<content type='text'>
Prepare for linking setup_sata only when CONFIG_SATA/CONFIG_SPL_SATA
is defined.

Signed-off-by: Troy Kisky &lt;troykiskyboundary@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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