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<title>u-boot.git/board/stxssa, branch v2009.08</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board/stxssa?h=v2009.08</id>
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<updated>2009-03-20T21:39:12Z</updated>
<entry>
<title>Fix all linker script to handle all rodata sections</title>
<updated>2009-03-20T21:39:12Z</updated>
<author>
<name>Trent Piepho</name>
<email>xyzzy@speakeasy.org</email>
</author>
<published>2009-02-18T23:22:05Z</published>
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<id>urn:sha1:f62fb99941c625605aa16a0097b396a5c16d2c88</id>
<content type='text'>
A recent gcc added a new unaligned rodata section called '.rodata.str1.1',
which needs to be added the the linker script.  Instead of just adding this
one section, we use a wildcard ".rodata*" to get all rodata linker section
gcc has now and might add in the future.

However, '*(.rodata*)' by itself will result in sub-optimal section
ordering.  The sections will be sorted by object file, which causes extra
padding between the unaligned rodata.str.1.1 of one object file and the
aligned rodata of the next object file.  This is easy to fix by using the
SORT_BY_ALIGNMENT command.

This patch has not be tested one most of the boards modified.  Some boards
have a linker script that looks something like this:

*(.text)
. = ALIGN(16);
*(.rodata)
*(.rodata.str1.4)
*(.eh_frame)

I change this to:

*(.text)
. = ALIGN(16);
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))

This means the start of rodata will no longer be 16 bytes aligned.
However, the boundary between text and rodata/eh_frame is still aligned to
16 bytes, which is what I think the real purpose of the ALIGN call is.

Signed-off-by: Trent Piepho &lt;xyzzy@speakeasy.org&gt;
</content>
</entry>
<entry>
<title>fsl-ddr: use the 1T timing as default configuration</title>
<updated>2009-01-23T23:03:14Z</updated>
<author>
<name>Dave Liu</name>
<email>daveliu@freescale.com</email>
</author>
<published>2008-11-21T08:31:43Z</published>
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<id>urn:sha1:b4983e16d150ab7d039704c310aacbd2f4dc1e0f</id>
<content type='text'>
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.

Signed-off-by: Dave Liu &lt;daveliu@freescale.com&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>Align end of bss by 4 bytes</title>
<updated>2008-11-18T22:13:16Z</updated>
<author>
<name>Selvamuthukumar</name>
<email>selva.muthukumar@e-coninfotech.com</email>
</author>
<published>2008-10-16T17:24:03Z</published>
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<id>urn:sha1:9b827cf1720acda2473afa516956eab6f7cca9a1</id>
<content type='text'>
Most of the bss initialization loop increments 4 bytes
at a time. And the loop end is checked for an 'equal'
condition. Make the bss end address aligned by 4, so
that the loop will end as expected.

Signed-off-by: Selvamuthukumar &lt;selva.muthukumar@e-coninfotech.com&gt;
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>Pass dimm parameters to populate populate controller options</title>
<updated>2008-10-18T19:54:04Z</updated>
<author>
<name>Haiying Wang</name>
<email>Haiying.Wang@freescale.com</email>
</author>
<published>2008-10-03T16:36:55Z</published>
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<id>urn:sha1:dfb49108e4f86c2224e1f30124328b0de66ef72e</id>
<content type='text'>
Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.

* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.

Signed-off-by: Haiying Wang &lt;Haiying.Wang@freescale.com&gt;
</content>
</entry>
<entry>
<title>rename CFG_ macros to CONFIG_SYS</title>
<updated>2008-10-18T19:54:03Z</updated>
<author>
<name>Jean-Christophe PLAGNIOL-VILLARD</name>
<email>plagnioj@jcrosoft.com</email>
</author>
<published>2008-10-16T13:01:15Z</published>
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<id>urn:sha1:6d0f6bcf337c5261c08fabe12982178c2c489d76</id>
<content type='text'>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</content>
</entry>
<entry>
<title>Coding style cleanup, update CHANGELOG</title>
<updated>2008-09-13T00:23:05Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2008-09-13T00:23:05Z</published>
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<id>urn:sha1:f12e4549b6fb01cd2654348af95a3c7a6ac161e7</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>Moved initialization of TULIP Ethernet controller to board_eth_init()</title>
<updated>2008-09-03T04:18:18Z</updated>
<author>
<name>Ben Warren</name>
<email>biggerbadderben@gmail.com</email>
</author>
<published>2008-08-31T17:45:44Z</published>
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<id>urn:sha1:8ca0b3f99c4fce7a599dcaf92ae095496dc8c8e0</id>
<content type='text'>
Affected boards:
	cu824
	bab7xx
	adciop
	dasa_sim
	mousse
	mpc8540eval
	musenki
	mvblue
	pcippc2/pcippc6
	sbc8240
	stxssa

Removed initialization of the driver from net/eth.c

Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</content>
</entry>
<entry>
<title>FSL DDR: Convert STXSSA to new DDR code.</title>
<updated>2008-08-27T16:43:53Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-08-27T06:04:07Z</published>
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<id>urn:sha1:0e7927db138976469e7257e29c1338050a50fcd9</id>
<content type='text'>
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>Cleanup out-or-tree building for some boards (.depend)</title>
<updated>2008-07-02T21:49:18Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2008-07-02T21:49:18Z</published>
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<id>urn:sha1:c8a3b109f07f02342d097b30908965f7261d9f15</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>Change initdram() return type to phys_size_t</title>
<updated>2008-06-12T06:50:18Z</updated>
<author>
<name>Becky Bruce</name>
<email>becky.bruce@freescale.com</email>
</author>
<published>2008-06-09T21:03:40Z</published>
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<id>urn:sha1:9973e3c614721bbf169882ffc3be266a6611cd60</id>
<content type='text'>
This patch changes the return type of initdram() from long int to phys_size_t.
This is required for a couple of reasons: long int limits the amount of dram
to 2GB, and u-boot in general is moving over to phys_size_t to represent the
size of physical memory.  phys_size_t is defined as an unsigned long on almost
all current platforms.

This patch *only* changes the return type of the initdram function (in
include/common.h, as well as in each board's implementation of initdram).  It
does not actually modify the code inside the function on any of the platforms;
platforms which wish to support more than 2GB of DRAM will need to modify
their initdram() function code.

Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc
MPC8641HPCN.

Signed-off-by: Becky Bruce &lt;becky.bruce@freescale.com&gt;
</content>
</entry>
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