u-boot.git/board/synopsys, branch v2017.05

axs103: Support slave core kick-start on axs103 v1.1 firmware

2017-03-31T19:09:36+00:00

In axs103 v1.1 procedure to kick-start slave cores has changed quite a bit
compared t previous implementation.

In particular:
 * We used to have a generic START bit for all cores selected by CORE_SEL
   mask. But now we don't touch CORE_SEL at all because we have a dedicated
   START bit for each core:
     bit 0: Core 0 (master)
     bit 1: Core 1 (slave)
 * Now there's no need to select "manual" mode of core start

Additional challenge for us is how to tell which axs103 firmware we're
dealing with. For now we'll rely on ARC core version which was bumped
from 2.1c to 3.0.

Signed-off-by: Alexey Brodkin

axs103: Clean-up smp_kick_all_cpus()

2017-03-31T19:09:36+00:00

 * Rely on default pulse polarity value
 * Don't mess with "multicore" value as it doesn't affect execution

In essence we now do a bare minimal stuff:
 1) Select HS38x2_1 with CORE_SEL=1 bits
 2) Select "manual" core start (via CREG) with START_MODE=0
 3) Generate cpu_start pulse with START=1

Signed-off-by: Alexey Brodkin

arc: dts: separate single axs10x.dts file

2017-03-24T11:47:52+00:00

We want to use the same device tree blobs in both Linux and U-Boot for
ARC boards.

Earlier device tree sources in U-Boot were very simplified and hadn't been
updated for quite a long period of time.

So this commit is the first step on the road to unified device tree blobs.

First of all we re-organize device tree sources for AXS10X boards.
As AXS101 and AXS103 boards consist of AXS10X motherboard and AXC001 and
AXC003 cpu tiles respectively we add corresponding device tree source
files: axs10x_mb.dtsi for motherboard, axc001.dtsi and axc003.dtsi for
cpu tiles and axs101.dts and axs103.dts to represent actual boards.

Also we delete axs10x.dts as it is no longer used.

One more important change - we add timer device to ARC skeleton device
tree sources as both ARC700 and ARCHS cores contain such timer.
We add core_clk nodes to abilis_tb100, nsim, axc001 and axc003 device tree
sources as it is referenced via phandle from timer node in common
skeleton.dtsi file.

Signed-off-by: Vlad Zakharov 
Reviewed-by: Simon Glass

arc: Rename AXS101 board to more generic AXS10x

2016-08-05T09:50:33+00:00

As of now we have 2 flavors of ARC SDP boards:
 1) AXS101 - with ARC770 in ASIC
 2) AXS103 - with ARC HS38 in FPGA

Both options share exactly the same base-board and only differ with
CPU-tiles in use. That means all peripherals are the same (they are
implemented in FPGA on the base-board) and so generic board could be
used for both.

While at it:
 * Recreated defconfigs with savedefconfig
 * In include/configs/axs10x.h numerical sizes replaced with
defines from linux/sizes.h for better readability.

Signed-off-by: Alexey Brodkin 
Reviewed-by: Tom Rini

arc: Rename ARCangel4 board to nSIM

2016-08-05T09:50:25+00:00

ARCangel was one of the main development boards back in the day but
now it's gone and replaced by other boards like ARC SDP.

But we also used to have simulation platform very similar to ARCangel4
in terms of CPU settings as well as basic IO like UART. Even though
ARCangel4 is long gone now we have a replacement for simulation which is
a plain or stand-alone nSIM and Free nSIM.

Note Free nSIM is available for download here:
https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi

And while at it:
 * Finally switch hex numerical values in nsim.h to defines from
   include/linux/sizes.h
 * Add defconfigs with ARC HS38 cores
 * Recreated all defconfigs with savedefconfig

Signed-off-by: Alexey Brodkin

board: axs10x: Flush entire cache after programming reset vector

2016-06-13T12:38:05+00:00

Now when we have support of IOC (IO-Coherency block) cahce operations
on regions are tuned to not be dummy stubs if IOC was found and enabled
in the core. That makes flush_dcache_range() useless for our purposes
here. And since we do need to flush modified reset vector to at least L2
cache (AKA SLC) so other cores will see it via its L1 instruction cache
we're using always functional flush_dcache_all() here.

Signed-off-by: Alexey Brodkin 
Cc: Marek Vasut

board: axs10x switch serial port and Ethernet to driver model

2015-11-17T21:39:22+00:00

With this change Synopsys DesignWare SDP board is switched to driver
model for both serial port (serial_dw) and Ethernet (Designware GMAC).

This simplifies include/configs/axs101.h and allows for reuse of Linux's
Device Tree description.

For simplicity Linux's .dts files are not blindly copied but only very
few extracts of them are really used (those that are supported in U-Boot
at the moment).

Signed-off-by: Alexey Brodkin 
Reviewed-by: Simon Glass 
Cc: Masahiro Yamada

board: axs10x - cap max SDIO clock value to bus/2

2015-10-07T15:16:13+00:00

It turned out with some boards (FPGA firmwares?) and cards combos
current clock settings doesn't work as expected leading to strange
card freezes or corrupted data being read from the card.

Especially this was seen with Transcend 2Gb cards shipped as a part of
ARC SDP:
----------------->8---------------
AXS# mmcinfo
Device: Synopsys Mobile storage
Manufacturer ID: 74
OEM: 4a60
Name: SDC
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0
High Capacity: No
Capacity: 1.8 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
AXS# fatload mmc 0
** Unrecognized filesystem type **
----------------->8---------------

With this change that problem is fixed.
Note "Tran Speed" above doesn't match clock value set in DW MMC.
It is max value for card's speed class.

Signed-off-by: Alexey Brodkin

board: axs103 - add maintainer information

2015-07-01T14:19:33+00:00

Looks like I forgot to add myself as a maintainer for AXS103 defconfig.
Fixing this now.

Signed-off-by: Alexey Brodkin 
Cc: Tom Rini

arc: implement slave cores kick-start for Linux kernel

2015-07-01T14:17:27+00:00

With new SMP-enabled CPUs with ARC HS38 cores and corresponding support
in Linux kernel it's required to add basic SMP support in U-Boot.

Currently we assume the one and only core starts execution after
power-on. So most of things in U-Boot is handled in UP mode.

But when U-Boot is used for loading and starting Linux kernel right
before jumping to kernel's entry point U-Boot:
 [1] Sets all slave cores to jump to the same address [kernel's entry
point]
 [2] Really starts all slav cores

In ARC's implemetation of SMP in Linux kernel all cores are supposed to
run the same start-up code. But only core with ID 0 (master core)
processes further while others are looping waiting for master core to
complete some initialization.

That means it's safe to un-pause slave cores and let them execute kernel
- they will wait for master anyway.

Signed-off-by: Alexey Brodkin 
Cc: Vineet Gupta