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<title>u-boot.git/board/ti, branch v2016.05</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board/ti?h=v2016.05</id>
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<updated>2016-04-25T19:10:41Z</updated>
<entry>
<title>ARM: DRA7: Add ABB setup for all domains</title>
<updated>2016-04-25T19:10:41Z</updated>
<author>
<name>Nishanth Menon</name>
<email>nm@ti.com</email>
</author>
<published>2016-04-21T19:34:25Z</published>
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<id>urn:sha1:e52e334e5cb493e19377d23a00aa4d021fc229ba</id>
<content type='text'>
ABB should be initialized for all required domains voltage domain
for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If
we do not do this, kernel configuring just the frequency using the
default boot loader configured voltage can fail on many corner lot
units and has been hard to debug. This specifically is a concern with
DRA7 generation of SoCs since other than VDD_MPU, all other domains
are only permitted to setup the voltages to required OPP only at boot.

Reported-by: Richard Woodruff &lt;r-woodruff2@ti.com&gt;
Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
</content>
</entry>
<entry>
<title>ARM: OMAP5/DRA7: Move ABB TXDONE mask to voltage structure</title>
<updated>2016-04-25T19:10:39Z</updated>
<author>
<name>Nishanth Menon</name>
<email>nm@ti.com</email>
</author>
<published>2016-04-21T19:34:23Z</published>
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<id>urn:sha1:3708e78c33b3853e300a6ded3113de90dacbc633</id>
<content type='text'>
ABB TX_DONE mask will vary depending on ABB module. For example,
3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain,
DRA7 has it on all domains with the exception of CORE, RTC.

Hence, move the txdone mask definition over to structure describing
voltage domain.

Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
</content>
</entry>
<entry>
<title>memory: Move TI_AEMIF config to KCONFIG</title>
<updated>2016-04-18T21:11:43Z</updated>
<author>
<name>Lokesh Vutla</name>
<email>lokeshvutla@ti.com</email>
</author>
<published>2016-04-13T04:20:59Z</published>
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<id>urn:sha1:8f69523213a2929fda1fb62fe018684444586c1b</id>
<content type='text'>
Not all Keystone2 devices has AEMIF NAND controller. So adding Kconfig
entry for CONFIG_TI_AEMIF and enabling it in respective defconfigs on
platforms with AEMIF controller.

Reported-by: Nishanth Menon &lt;nm@ti.com&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>board: ti: am57xx: Add support for am572x idk in SPL</title>
<updated>2016-04-18T21:11:32Z</updated>
<author>
<name>Steve Kipisz</name>
<email>s-kipisz2@ti.com</email>
</author>
<published>2016-04-08T22:01:29Z</published>
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<id>urn:sha1:c020d355c45ed40fe12af72ae5487527167fafd5</id>
<content type='text'>
The AM572x-IDK board (Industrial Dev Kit) is a board based on TI's AM5728x
SOC which has a dual core 1.5GHz A15 processor. This board is a development
platform for the Industrial market with:
- 2GB of DDR3L
- Dual 1Gbps Ethernet
- HDMI,
- PRU-ICSS
- uSD
- 16GB eMMC
- CAN
- RS-485
- PCIe
- USB3.0
- Video Input Port
- Industrial IO port and expansion connector

The link to the data sheet and TRM can be found here:

http://www.ti.com/product/AM5728

NOTE: DT support is still pending upstream kernel acceptance but we
should be able to get the base system support with this patch.

Signed-off-by: Schuyler Patton &lt;spatton@ti.com&gt;
Signed-off-by: Steve Kipisz &lt;s-kipisz2@ti.com&gt;
Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
Reviewed-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings</title>
<updated>2016-04-18T21:11:32Z</updated>
<author>
<name>Schuyler Patton</name>
<email>spatton@ti.com</email>
</author>
<published>2016-04-08T21:53:44Z</published>
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<id>urn:sha1:5f405e7fa0c4baf4cc57a82d2fcddb86789cfaed</id>
<content type='text'>
Update EMIF data based on recommendations from the now standard TI
EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB
data sheet

Update T_RRD from 5 to 6 based on AM57xx TRM -
Minimum number of DDR cycles from activate to ativate for a different
bank, minus 1.

Update T_CKESR from 4 to 3 based on AM57xx TRM - Minimum number of DDR
clocks cycles for which SDRAM must remain in self refresh, minus 1.

Signed-off-by: Schuyler Patton &lt;spatton@ti.com&gt;
Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
Reviewed-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>am57x: Move CONS_INDEX to Kconfig</title>
<updated>2016-04-18T21:11:31Z</updated>
<author>
<name>Daniel Allred</name>
<email>d-allred@ti.com</email>
</author>
<published>2016-04-07T02:59:34Z</published>
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<id>urn:sha1:7e52e11f3537809e48a6e337c392a1289a692061</id>
<content type='text'>
- Move the CONS_INDEX selection out of CONFIG_SYS_EXTRA_OPTIONS and
      into Kconfig proper.
    - Edit the relevant am57x configs to remove the now unneeded
      CONFIG_SYS_EXTRA_OPTIONS.

Signed-off-by: Daniel Allred &lt;d-allred@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>board: ti: am57xx: Prevent init_sata() from being called twice</title>
<updated>2016-04-12T00:48:21Z</updated>
<author>
<name>Roger Quadros</name>
<email>rogerq@ti.com</email>
</author>
<published>2016-04-04T07:53:31Z</published>
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<id>urn:sha1:c3333ded03b4868c42b0eefd4a3e97c14e0d1f57</id>
<content type='text'>
init_sata() is done as part of scsi_init() in
arch/arm/cpu/armv7/omap-common/sata.c so no need to duplicate
it here.

This seems to fix SATA problems in the kernel when CONFIG_TI_PIPE3 is
configured as loadable module.

Cc: Cooper Jr., Franklin &lt;fcooper@ti.com&gt;
Cc: Nishanth Menon &lt;nm@ti.com&gt;
Signed-off-by: Roger Quadros &lt;rogerq@ti.com&gt;
</content>
</entry>
<entry>
<title>board: ti: DRA7: Add DP83867 TI phy for rev c</title>
<updated>2016-04-01T21:18:07Z</updated>
<author>
<name>Dan Murphy</name>
<email>dmurphy@ti.com</email>
</author>
<published>2016-03-30T17:58:37Z</published>
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<id>urn:sha1:39fbac91e1987b6c4d7699d2adef41cb65bb7c96</id>
<content type='text'>
Enable the TI DP83867 Giga bit phy on the
dra7 rev c board.  The rx and tx internal
delays are need for this board so the usage
of RGMII_ID is required.

Signed-off-by: Dan Murphy &lt;dmurphy@ti.com&gt;
Acked-by: Mugunthan V N &lt;mugunthanvnm@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>board: ti: am57xx: Set ethernet MAC addresses from EEPROM to env</title>
<updated>2016-03-27T13:12:27Z</updated>
<author>
<name>Roger Quadros</name>
<email>rogerq@ti.com</email>
</author>
<published>2016-03-18T11:18:12Z</published>
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<id>urn:sha1:92667e89fc5906531a7a1ff247e1ffec61b55b13</id>
<content type='text'>
The MAC addresses for the PRU Ethernet ports will be available in the
board EEPROM as an address range. Populate those MAC addresses (if valid)
into the u-boot environment so that they can be passed on to the
device tree during fdt_fixup_ethernet().

Signed-off-by: Roger Quadros &lt;rogerq@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>board: ti: DRA7: Add DRA72-rev C evm pinmux</title>
<updated>2016-03-27T13:12:16Z</updated>
<author>
<name>Nishanth Menon</name>
<email>nm@ti.com</email>
</author>
<published>2016-03-15T23:09:17Z</published>
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<id>urn:sha1:8cac14719d5bc6a71cd249b349331fe5f2ffa03f</id>
<content type='text'>
Add the pinmux data for rev C evm. This is different from previous
revisions of the platform thanks to the deltas introduced both from
silicon side and from SoC side.

Based on J6EcoES2_EVM_Base_Config-20160309b and PCT-DRA72x-v1.3.0.7 for
SR2.0 silicon.

Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
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