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<title>u-boot.git/board/toradex, branch v2018.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board/toradex?h=v2018.09</id>
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<updated>2018-09-04T06:47:23Z</updated>
<entry>
<title>colibri_imx7_emmc: add Colibri iMX7D 1GB (eMMC) module support</title>
<updated>2018-09-04T06:47:23Z</updated>
<author>
<name>Stefan Agner</name>
<email>stefan.agner@toradex.com</email>
</author>
<published>2018-08-06T07:19:19Z</published>
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<id>urn:sha1:a62c60610f514063ac71f8835b47d413972256b8</id>
<content type='text'>
This commit adds support for the Toradex Colibri iMX7D 1GB Computer
on Module. The module is very similar to the Colibri iMX7D 512MB
but uses eMMC instead of raw NAND. This patch introduces a new
board specific Kconfig symbol to select between the two flash
options.

Signed-off-by: Stefan Agner &lt;stefan.agner@toradex.com&gt;
</content>
</entry>
<entry>
<title>board: toradex: common: fail gracefully on missing NAND chip</title>
<updated>2018-09-04T06:47:23Z</updated>
<author>
<name>Stefan Agner</name>
<email>stefan.agner@toradex.com</email>
</author>
<published>2018-08-06T07:19:18Z</published>
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<id>urn:sha1:bc53fb19fef1afbd7b328ea72de5be313016f585</id>
<content type='text'>
If the NAND chip is missing get_nand_dev_by_index() returns NULL. Fail
gracefully in this case.

Signed-off-by: Stefan Agner &lt;stefan.agner@toradex.com&gt;
</content>
</entry>
<entry>
<title>board: constify struct node_info array</title>
<updated>2018-07-24T23:47:52Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2018-07-19T07:28:23Z</published>
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<id>urn:sha1:b35fb6ace67202b6f668f744f958a5ef66665151</id>
<content type='text'>
Add 'const' (also 'static' in some places) to struct node_info
arrays to save memory footprint.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>colibri_imx7: improve DDR3 timing</title>
<updated>2018-07-23T08:56:38Z</updated>
<author>
<name>Stefan Agner</name>
<email>stefan.agner@toradex.com</email>
</author>
<published>2018-06-26T09:10:52Z</published>
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<id>urn:sha1:a19797b22cbc955ade2ef59c78fbdeea866285a9</id>
<content type='text'>
This makes sure that all Colibri iMX7 modules work with the
same timing. The changes are:
- Disable ODT on read (JEDEC standard JESD79-3F says in chapter
  5.2.3 ODT during Reads: "As the DDR3 SDRAM can not terminate
  and drive at the same time, RTT must be disabled at least half
  a clock cycle..." and also MX7D SABRESD is disabling it)
  This alone fixed memory issues for two Colibri iMX7 1GB modules
  which showed issues before
- Make sure tRFC(min) is at least 260ns
- Make sure tRC is &gt;50.625ns
- tRP needs to be &gt;13.125ns, we can lower from 18.75ns to 15ns
- tFAW is not relevant, leave at reset

Signed-off-by: Stefan Agner &lt;stefan.agner@toradex.com&gt;
Acked-by: Marcel Ziswiler &lt;marcel.ziswiler@toradex.com&gt;
</content>
</entry>
<entry>
<title>colibri_imx7: add compatible string used in vanilla Linux</title>
<updated>2018-07-23T08:56:27Z</updated>
<author>
<name>Stefan Agner</name>
<email>stefan.agner@toradex.com</email>
</author>
<published>2018-06-26T09:10:51Z</published>
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<id>urn:sha1:e38adcecca4731acaa51b37b00ee5feee55b6b85</id>
<content type='text'>
Device trees from vanilla Linux do not specify a i.MX 7 specific
compatible string. Make sure to set partitions also when booting
upstream Linux.

Signed-off-by: Stefan Agner &lt;stefan.agner@toradex.com&gt;
</content>
</entry>
<entry>
<title>mx7: Remove BMODE support</title>
<updated>2018-07-23T08:50:00Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2018-06-22T16:54:55Z</published>
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<id>urn:sha1:2756d31fae31da75f3ac8a10a61e6dd0ebea79c8</id>
<content type='text'>
i.MX7 does not support BMODE due to the erratum e10574 ("Watchdog:
A watchdog timeout or software trigger will not reset the SOC"), so
remove its support.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
</content>
</entry>
<entry>
<title>board: toradex: add Colibri iMX6ULL support</title>
<updated>2018-07-23T08:12:00Z</updated>
<author>
<name>Stefan Agner</name>
<email>stefan.agner@toradex.com</email>
</author>
<published>2018-05-30T17:01:48Z</published>
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<id>urn:sha1:31b1e17f444c013083d6b09864f2f63067506492</id>
<content type='text'>
Add support for the Colibri iMX6ULL module which comes with
on-board raw NAND.

Signed-off-by: Stefan Agner &lt;stefan.agner@toradex.com&gt;
</content>
</entry>
<entry>
<title>board: toradex: add new and upcoming SKUs</title>
<updated>2018-07-23T08:12:00Z</updated>
<author>
<name>Stefan Agner</name>
<email>stefan.agner@toradex.com</email>
</author>
<published>2018-05-30T17:01:47Z</published>
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<id>urn:sha1:d826b8751925aa535fd692f157b6d0dbfbea490a</id>
<content type='text'>
Signed-off-by: Stefan Agner &lt;stefan.agner@toradex.com&gt;
</content>
</entry>
<entry>
<title>apalis_t30: fix optional pcie port reset for reliable pcie operation</title>
<updated>2018-05-10T23:34:30Z</updated>
<author>
<name>Marcel Ziswiler</name>
<email>marcel.ziswiler@toradex.com</email>
</author>
<published>2018-05-08T22:18:40Z</published>
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<id>urn:sha1:71cb3d7c7897cd02ca731f4c510fff49705b84b7</id>
<content type='text'>
Allow optionally bringing up the Apalis type specific 4 lane PCIe port
as well as the PCIe switch as found on the Apalis Evaluation board. In
order to avoid violating the PCIe reset timing do this by overriding the
tegra_pcie_board_port_reset() function. Note however that both the
Apalis type specific 4 lane PCIe port as well as the regular Apalis PCIe
port are also left disabled in the device tree by default.

Signed-off-by: Marcel Ziswiler &lt;marcel.ziswiler@toradex.com&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>apalis_t30: fix pcie port 0 and 1 pin muxing</title>
<updated>2018-05-10T23:34:30Z</updated>
<author>
<name>Marcel Ziswiler</name>
<email>marcel.ziswiler@toradex.com</email>
</author>
<published>2018-05-08T22:18:39Z</published>
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<id>urn:sha1:b4f901042807e59061a862adc265d8f899b2243f</id>
<content type='text'>
Fix optional Apalis type specific 4 lane PCIe port 0 and Apalis PCIe
port 1 pin muxing.

Signed-off-by: Marcel Ziswiler &lt;marcel.ziswiler@toradex.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
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