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<title>u-boot.git/board/tqc, branch v2009.06</title>
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<id>http://cgit.235523.xyz/u-boot.git/atom/board/tqc?h=v2009.06</id>
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<updated>2009-06-03T22:16:16Z</updated>
<entry>
<title>Redundant Environment: protect full sector size</title>
<updated>2009-06-03T22:16:16Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2009-05-14T22:16:03Z</published>
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<id>urn:sha1:dfcd7f21607fd847236b04bb1a8d59a7c10ab99c</id>
<content type='text'>
Several boards used different ways to specify the size of the
protected area when enabling flash write protection for the sectors
holding the environment variables: some used CONFIG_ENV_SIZE and
CONFIG_ENV_SIZE_REDUND, some used CONFIG_ENV_SECT_SIZE, and some even
a mix of both for the "normal" and the "redundant" areas.

Normally, this makes no difference at all. However, things are
different when you have to deal with boards that can come with
different types of flash chips, which may have different sector
sizes.

Here we may have to chose CONFIG_ENV_SECT_SIZE such that it fits the
biggest sector size, which may include several sectors on boards using
the smaller sector flash types. In such a case, using CONFIG_ENV_SIZE
or CONFIG_ENV_SIZE_REDUND to enable the protection may lead to the
case that only the first of these sectors get protected, while the
following ones aren't.

This is no real problem, but it can be confusing for the user -
especially on boards that use CONFIG_ENV_SECT_SIZE to protect the
"normal" areas, while using CONFIG_ENV_SIZE_REDUND for the
"redundant" area.

To avoid such inconsistencies, I changed all sucn boards that I found
to consistently use CONFIG_ENV_SECT_SIZE for protection. This should
not cause any functional changes to the code.

Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Paul Ruhland
Cc: Pantelis Antoniou &lt;panto@intracom.gr&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Gary Jennejohn &lt;garyj@denx.de&gt;
Cc: Dave Ellis &lt;DGE@sixnetio.com&gt;
Acked-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>fsl_pci: Move prototypes into fsl_pci.h and remove explicit externs</title>
<updated>2009-04-04T15:21:30Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2009-04-02T18:57:05Z</published>
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<id>urn:sha1:32049b4048ff8e59bd5ba6160d6d5206d283b2a2</id>
<content type='text'>
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>fsl_pci: Renamed immap_fsl_pci.h to fsl_pci.h</title>
<updated>2009-04-04T15:21:29Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2009-04-02T18:22:48Z</published>
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<id>urn:sha1:c8514622e2713d9c47919acfe23fce386782afe7</id>
<content type='text'>
Rename the pci header for FSL HW so we can move some prototypes
in there and stop doing explicit externs

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>Add multi-chip NAND support for the TQM8548 modules</title>
<updated>2009-03-23T20:53:41Z</updated>
<author>
<name>Wolfgang Grandegger</name>
<email>wg@grandegger.com</email>
</author>
<published>2009-02-11T17:38:24Z</published>
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<id>urn:sha1:16f2f5a351004129e79e79816697a367fd9e5446</id>
<content type='text'>
This patches configures the NAND UPM-FSL driver with multi-chip
support for the Micron MT29F8G08FAB NAND flash memory on the
TQM8548 modules.

Signed-off-by: Wolfgang Grandegger &lt;wg@grandegger.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
</entry>
<entry>
<title>Fix all linker script to handle all rodata sections</title>
<updated>2009-03-20T21:39:12Z</updated>
<author>
<name>Trent Piepho</name>
<email>xyzzy@speakeasy.org</email>
</author>
<published>2009-02-18T23:22:05Z</published>
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<id>urn:sha1:f62fb99941c625605aa16a0097b396a5c16d2c88</id>
<content type='text'>
A recent gcc added a new unaligned rodata section called '.rodata.str1.1',
which needs to be added the the linker script.  Instead of just adding this
one section, we use a wildcard ".rodata*" to get all rodata linker section
gcc has now and might add in the future.

However, '*(.rodata*)' by itself will result in sub-optimal section
ordering.  The sections will be sorted by object file, which causes extra
padding between the unaligned rodata.str.1.1 of one object file and the
aligned rodata of the next object file.  This is easy to fix by using the
SORT_BY_ALIGNMENT command.

This patch has not be tested one most of the boards modified.  Some boards
have a linker script that looks something like this:

*(.text)
. = ALIGN(16);
*(.rodata)
*(.rodata.str1.4)
*(.eh_frame)

I change this to:

*(.text)
. = ALIGN(16);
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))

This means the start of rodata will no longer be 16 bytes aligned.
However, the boundary between text and rodata/eh_frame is still aligned to
16 bytes, which is what I think the real purpose of the ALIGN call is.

Signed-off-by: Trent Piepho &lt;xyzzy@speakeasy.org&gt;
</content>
</entry>
<entry>
<title>boards: get mac address from env and move load_sernum_ethaddr() to board init</title>
<updated>2009-03-20T21:39:12Z</updated>
<author>
<name>Mike Frysinger</name>
<email>vapier@gentoo.org</email>
</author>
<published>2009-02-12T01:09:52Z</published>
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<id>urn:sha1:9c150102bc1de375d36d97a1cc2dd0e9639b15df</id>
<content type='text'>
The environment is the canonical storage location of the mac address, so
we're killing off the global data location and moving everything to
querying the env directly.

Rather than have common ppc code call a board-specific function like
load_sernum_ethaddr(), have each board call it in its own board-specific
misc_init_r() function.

The boards that get converted here are:
	- kup4k/kup4x
	- pcs440ep
	- tqm8xx

Signed-off-by: Mike Frysinger &lt;vapier@gentoo.org&gt;
CC: Ben Warren &lt;biggerbadderben@gmail.com&gt;
CC: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>TQM8xxL: make some room in low memory for future needs</title>
<updated>2009-02-19T13:01:42Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2009-02-19T12:53:29Z</published>
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<id>urn:sha1:32482be67775e00b4cbc49fba62347c1ecc6229c</id>
<content type='text'>
THe TQM8xxL use a ahnd-optimized linker script to efficiently use the
small boot sectors in the flash. This patch makes some room in the
first sector to prepare for a size increase of lib_generic/vsprintf.o
by a future patch.

Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>TQM85xx: Fix a couple warnings in TQM8548 build</title>
<updated>2009-02-17T00:06:03Z</updated>
<author>
<name>Andy Fleming</name>
<email>afleming@freescale.com</email>
</author>
<published>2009-02-16T15:40:20Z</published>
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<id>urn:sha1:e0c4fac79d4d74572ddd43f75e7189cecca8d0ad</id>
<content type='text'>
The ecm variable in sdram.c was being declared for all 8548, but only
used by specific 8548 boards, so we make that variable require those
specific boards, too

The nand code was using an index "i" into a table, and then re-using "i"
to set addresses for each upm.  However, then it relied on the old value
of i still being there to enable things.  Changed the second "i" to "j"

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>MPC85xx: TQM8548: workaround for erratum DDR 19 and 20</title>
<updated>2009-02-17T00:06:02Z</updated>
<author>
<name>Wolfgang Grandegger</name>
<email>wg@grandegger.com</email>
</author>
<published>2009-02-11T17:38:26Z</published>
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<id>urn:sha1:cf07a5baece0ecfc5284cfda8a4e68eaf92782f8</id>
<content type='text'>
This patch adds the workaround for erratum DDR20 according to MPC8548
Device Errata document, Rev. 1: "CKE signal may not function correctly
after assertion of HRESET". Furthermore, the bug DDR19 is fixed in
processor version 2.1 and the work-around must be removed.

Signed-off-by: Wolfgang Grandegger &lt;wg@grandegger.com&gt;
</content>
</entry>
<entry>
<title>MPC85xx: TQM8548: use cache for AG and BE variants</title>
<updated>2009-02-17T00:06:02Z</updated>
<author>
<name>Wolfgang Grandegger</name>
<email>wg@grandegger.com</email>
</author>
<published>2009-02-11T17:38:25Z</published>
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<id>urn:sha1:080408fdc71706adcb883d22125637c54f6010b1</id>
<content type='text'>
This patch makes accesses to the system memory cachable by removing the
caching-inhibited and guarded flags from the relevant TLB entries for
the TQM8548_BE and TQM8548_AG modules. FYI, the Freescale MPC85* boards
are configured similarly.

This results in a big averall performace improvement. TFTP downloads,
NAND Flash accesses, kernel boots, etc. are much faster.

Signed-off-by: Wolfgang Grandegger &lt;wg@grandegger.com&gt;
</content>
</entry>
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